公开(公告)号：US20220138038A1

公开(公告)日：2022-05-05

申请号：US17575252

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Jonathan Scott Parry

IPC: G06F11/07

Abstract: In various embodiments, a technique can be provided to address debug efficiency for failures found on an operational system. The approach can make use of an existing pin on a memory device with added logic to respond to a trigger signal structured different from a signal that is normally sent to the existing pin on the memory device such that the memory device performs a normal or routine function of the memory device in response to the signal. In response to detecting one or more error conditions associated with the memory device, a system that interfaces with the memory device can generate the trigger signal to the memory device. In response to receiving the trigger signal, the memory device can dump an error log of the memory device to a memory component in the memory device. The error log can later be retrieved from the memory component for failure analysis.

公开(公告)号：US20210056021A1

公开(公告)日：2021-02-25

申请号：US16548107

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Jonathan Scott Parry ,  Nadav Grosz

IPC: G06F12/0804 ,  G06F3/06 ,  G06F12/02 ,  G06F12/10

Abstract: Devices and techniques for logical-to-physical (L2P) map (e.g., table) synchronization in a managed memory device are described herein. For example, a plaintext portion of an L2P map may be updated in a managed memory device. In response to updating the plaintext portion of the L2P map, the updated portion can be obfuscated to create an obfuscated version of the updated portion of the L2P map. Both the updated portion and the obfuscated version of the updated portion can be saved in storage of the memory device. When a request from a host for the updated portion of the L2P map is received, the memory device can provide the obfuscated version of the portion from the storage.

公开(公告)号：US20210026557A1

公开(公告)日：2021-01-28

申请号：US16521385

申请日：2019-07-24

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Jonathan Scott Parry

IPC: G06F3/06 ,  G06F12/06

Abstract: Systems and methods of memory operation involving dynamic adjustment of write policy based on performance needs are disclosed. In one embodiment, an exemplary method may comprise monitoring memory performance parameters related to a programming operation being scheduled, selecting a write policy based on the memory performance parameters monitored, executing a memory control process that is configured to switch between a first addressing scheme and a second addressing scheme, and programming a first superpage of the programming operation using the first addressing scheme and programing a second superpage of the programming operation using the second addressing scheme.

公开(公告)号：US20210018975A1

公开(公告)日：2021-01-21

申请号：US16511490

申请日：2019-07-15

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Jonathan Scott Parry

IPC: G06F1/3287 ,  G06F1/28

Abstract: Systems and methods are disclosed, including, after a first threshold time after entering an idle power mode of a storage system, without receiving a command from a host device over a communication interface, moving host data stored in volatile memory of the storage system to non-volatile memory of the storage system and transitioning a power mode of the storage system from an idle power mode to a deep idle power mode using control circuitry of the storage system, the deep idle power mode having a second power level lower than a first power level of the idle mode and a second exit latency higher than a first latency of the idle mode. The control circuitry can further determine that the storage system is ready to enter a power savings power mode and provide an indication of the determination using a unidirectional power state signal interface separate from the communication interface.

公开(公告)号：US11994947B2

公开(公告)日：2024-05-28

申请号：US17884432

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Huai-Yuan Tseng ,  Mustafa N. Kaynak ,  Akira Goda ,  Sivagnanam Parthasarathy ,  Jonathan Scott Parry

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/0793

Abstract: A system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. Based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. The user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. Upon stress event completion, pages having user data with the extra error correction code data are scanned. If pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. The extra error correction code data is deleted from the second block and the second block is made available for user data.

公开(公告)号：US11847014B2

公开(公告)日：2023-12-19

申请号：US17853337

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Jonathan Scott Parry ,  Nadav Grosz

IPC: G06F11/07 ,  G06F9/445 ,  G06F1/3287 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3237

CPC classification number: G06F11/0757 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/445 ,  G06F11/076 ,  G06F2201/81

Abstract: Apparatus and methods are disclosed, including determining whether firmware has been successfully loaded and whether the firmware version is valid and operable, and if the firmware has not been successfully loaded or the firmware is not valid and operable, tracking a number of unsuccessful attempts to load the firmware or an elapsed time for unsuccessful attempts to load the firmware, and entering a memory device into a reduced-power state if either the number of unsuccessful attempts or the elapsed time has reached a programmable threshold.

公开(公告)号：US11829232B2

公开(公告)日：2023-11-28

申请号：US17575252

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Jonathan Scott Parry

IPC: G06F11/07

CPC classification number: G06F11/0778 ,  G06F11/0727 ,  G06F11/0757 ,  G06F11/0775

Abstract: In various embodiments, a technique can be provided to address debug efficiency for failures found on an operational system. The approach can make use of an existing pin on a memory device with added logic to respond to a trigger signal structured different from a signal that is normally sent to the existing pin on the memory device such that the memory device performs a normal or routine function of the memory device in response to the signal. In response to detecting one or more error conditions associated with the memory device, a system that interfaces with the memory device can generate the trigger signal to the memory device. In response to receiving the trigger signal, the memory device can dump an error log of the memory device to a memory component in the memory device. The error log can later be retrieved from the memory component for failure analysis.

公开(公告)号：US11656673B2

公开(公告)日：2023-05-23

申请号：US17136891

申请日：2020-12-29

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Jonathan Scott Parry ,  David Aaron Palmer ,  Stephen Hanna

IPC: G06F1/3234 ,  G06F3/06

CPC classification number: G06F1/3275 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0679

Abstract: A memory device includes a hardware suspend mechanism configured to place a component of a memory controller into a lower power mode while a memory operation is being completed. A timer is provided to wakeup the CPU out of the lower power mode; and hardware interrupts can be used in determining to either enter or wake from the lower power mode. Memory monitoring circuitry is provided to estimate the duration of memory operations; and timers are provided to wake the component in the absence of hardware interrupts or additional commands.

公开(公告)号：US20220350539A1

公开(公告)日：2022-11-03

申请号：US17865760

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Jonathan Scott Parry

IPC: G06F3/06 ,  G06F12/06

Abstract: Systems and methods of memory operation involving dynamic adjustment of write policy based on performance needs are disclosed. In one embodiment, an exemplary method may comprise monitoring memory performance parameters related to a programming operation being scheduled, selecting a write policy based on the memory performance parameters monitored, executing a memory control process that is configured to switch between the first addressing scheme and the second addressing scheme, and programming a first superpage of the programming operation using the first addressing scheme and programing a second superpage of the programming operation using the second addressing scheme.

公开(公告)号：US11435944B2

公开(公告)日：2022-09-06

申请号：US16521385

申请日：2019-07-24

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Jonathan Scott Parry

IPC: G06F3/06 ,  G06F12/06

Abstract: Systems and methods of memory operation involving dynamic adjustment of write policy based on performance needs are disclosed. In one embodiment, an exemplary method may comprise monitoring memory performance parameters related to a programming operation being scheduled, selecting a write policy based on the memory performance parameters monitored, executing a memory control process that is configured to switch between a first addressing scheme and a second addressing scheme, and programming a first superpage of the programming operation using the first addressing scheme and programing a second superpage of the programming operation using the second addressing scheme.