公开(公告)号：US20220392526A1

公开(公告)日：2022-12-08

申请号：US17337806

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Xuan Anh Tran ,  Karthik Sarpatwari ,  Francesco Douglas Verna-Ketel ,  Jessica Chen ,  Nevil N. Gajera ,  Amitava Majumdar

IPC: G11C11/56 ,  G11C13/00

Abstract: Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.

公开(公告)号：US20220383950A1

公开(公告)日：2022-12-01

申请号：US17332242

申请日：2021-05-27

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Lingming Yang ,  John F. Schreck

IPC: G11C13/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.

公开(公告)号：US11355554B2

公开(公告)日：2022-06-07

申请号：US16870239

申请日：2020-05-08

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera ,  Lei Wei

IPC: H01L29/06 ,  H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  H01L23/532

Abstract: An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.

公开(公告)号：US20210351234A1

公开(公告)日：2021-11-11

申请号：US16870239

申请日：2020-05-08

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera ,  Lei Wei

IPC: H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  H01L23/532

Abstract: An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.

公开(公告)号：US20210287744A1

公开(公告)日：2021-09-16

申请号：US17196638

申请日：2021-03-09

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Nevil Gajera ,  Karthik Sarpatwari

IPC: G11C13/00

Abstract: Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell.

公开(公告)号：US11114156B2

公开(公告)日：2021-09-07

申请号：US16660569

申请日：2019-10-22

Applicant: Micron Technology, Inc.

Inventor： Josephine Tiu Hamada ,  Kenneth Richard Surdyk ,  Lingming Yang ,  Mingdong Cui

IPC: G11C11/16 ,  G11C11/56 ,  G11C11/4074

Abstract: An integrated circuit memory device, having: a first wire; a second wire; a memory cell connected between the first wire and the second wire; a first voltage driver connected to the first wire; and a second voltage driver connected to the second wire. During an operation to read the memory cell, the second voltage driver is configured to start ramping up a voltage applied on the second wire after the first voltage driver starts ramping up and holding a voltage applied on the first wire.

公开(公告)号：US20210118497A1

公开(公告)日：2021-04-22

申请号：US16660569

申请日：2019-10-22

Applicant: Micron Technology, Inc.

Inventor： Josephine Tiu Hamada ,  Kenneth Richard Surdyk ,  Lingming Yang ,  Mingdong Cui

IPC: G11C11/56 ,  G11C11/4074

Abstract: An integrated circuit memory device, having: a first wire; a second wire; a memory cell connected between the first wire and the second wire; a first voltage driver connected to the first wire; and a second voltage driver connected to the second wire. During an operation to read the memory cell, the second voltage driver is configured to start ramping up a voltage applied on the second wire after the first voltage driver starts ramping up and holding a voltage applied on the first wire.