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公开(公告)号：US11157176B2
公开(公告)日：2021-10-26
申请号：US16419858
申请日：2019-05-22
Applicant: Micron Technology, Inc.
Inventor： Duane R. Mills , Richard E. Fackenthal
Abstract: Systems, devices, and methods related to on demand memory page size are described. A memory system may employ a protocol that supports on demand variable memory page sizes. A memory system may include one or more non-volatile memory devices that may each include a local memory controller configured to support variable memory page size operation. The memory system may include a system memory controller that interfaces between the non-volatile memory devices and a processor. The system memory controller may, for instance, use a protocol that facilitates on demand memory page size where a determination of a particular page size to use in an operation may be based on characteristics of memory commands and data involved in the memory command.
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公开(公告)号：US10855295B2
公开(公告)日：2020-12-01
申请号：US16859786
申请日：2020-04-27
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal , Daniele Vimercati , Jahanshir Javanifard
Abstract: Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.
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公开(公告)号：US10802909B2
公开(公告)日：2020-10-13
申请号：US16104470
申请日：2018-08-17
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal
Abstract: Methods, systems, and devices for operating memory cell(s) using an enhanced bit flipping scheme are described. An enhanced bit flipping scheme may include methods, systems, and devices for performing error correction of data bits in a codeword concurrently with the generation of a flip bit that indicates whether data bits in a corresponding codeword are to be flipped; for refraining from performing error correction of inversion bit(s) in the codeword; and for generating a high-reliability flip bit using multiple inversion bits. For instance, a flip bit that is even more reliable may be generated by determining whether a number of, a majority of, or all of the inversion bits indicate that the data bits are in an inverted state.
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公开(公告)号：US10770126B2
公开(公告)日：2020-09-08
申请号：US16448521
申请日：2019-06-21
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal
Abstract: A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.
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公开(公告)号：US20200259497A1
公开(公告)日：2020-08-13
申请号：US16859786
申请日：2020-04-27
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal , Daniele Vimercati , Jahanshir Javanifard
Abstract: Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.
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Patent Agency Ranking
公开(公告)号：US20200013478A1
公开(公告)日：2020-01-09
申请号：US16513018
申请日：2019-07-16
Applicant: Micron Technology, Inc.
Inventor： Simon J. Lovett , Richard E. Fackenthal
Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
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公开(公告)号：US20190339866A1
公开(公告)日：2019-11-07
申请号：US16419858
申请日：2019-05-22
Applicant: Micron Technology, Inc.
Inventor： Duane R. Mills , Richard E. Fackenthal
Abstract: Systems, devices, and methods related to on demand memory page size are described. A memory system may employ a protocol that supports on demand variable memory page sizes. A memory system may include one or more non-volatile memory devices that may each include a local memory controller configured to support variable memory page size operation. The memory system may include a system memory controller that interfaces between the non-volatile memory devices and a processor. The system memory controller may, for instance, use a protocol that facilitates on demand memory page size where a determination of a particular page size to use in an operation may be based on characteristics of memory commands and data involved in the memory command.
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公开(公告)号：US20190332281A1
公开(公告)日：2019-10-31
申请号：US16510236
申请日：2019-07-12
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal , Duane R. Mills
Abstract: In an example, a portion of a memory array may be selected to be wear leveled based on how often the portion is or is to be accessed. The portion may be wear leveled.
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公开(公告)号：US10403389B2
公开(公告)日：2019-09-03
申请号：US16001784
申请日：2018-06-06
Applicant: Micron Technology, Inc.
Inventor： Simon J. Lovett , Richard E. Fackenthal
Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
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公开(公告)号：US20190066752A1
公开(公告)日：2019-02-28
申请号：US15691454
申请日：2017-08-30
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal , Daniele Vimercati , Duane R. Mills
CPC classification number: G11C11/2253 , G06F11/1008 , G06F11/1048 , G11C11/221 , G11C11/2275 , G11C29/52
Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.
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