公开(公告)号：US11133075B2

公开(公告)日：2021-09-28

申请号：US16023386

申请日：2018-06-29

Applicant: Micron Technology, Inc.

Inventor： Greg A. Blodgett ,  Sebastien Andre Jean

IPC: G06F3/06 ,  G06F12/00 ,  G06F13/00 ,  G11C16/34 ,  G11C16/04 ,  G06F1/3206 ,  G11C7/04 ,  G06F12/14 ,  G06F9/30 ,  G06F9/32 ,  G06F9/54 ,  G06F12/02 ,  G06F21/79 ,  H04L9/08 ,  G06F1/3234 ,  G11C16/10

Abstract: Apparatus and methods are disclosed including a memory device or a memory controller configured to receive, from a host device over a host interface, a request for a device descriptor of a memory device, and to send to the host, over the host interface, the device descriptor, the device descriptor including voltage supply capability fields that are set to indicate supported voltages of the memory device, the supported voltages selected from a plurality of discrete voltages. The host device can utilize the supported voltages to supply an appropriate voltage to the memory device. Methods of operation are disclosed, as well as machine-readable medium, a host computing device, and other embodiments.

公开(公告)号：US11119933B2

公开(公告)日：2021-09-14

申请号：US16534710

申请日：2019-08-07

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F12/08 ,  G06F12/0871 ,  G06F9/54 ,  G06F9/50 ,  G06F12/02

Abstract: Disclosed in some examples are methods, systems, and machine readable mediums that dynamically adjust the size of an L2P cache in a memory device in response to observed operational conditions. The L2P cache may borrow memory space from a donor memory location, such as a read or write buffer. For example, if the system notices a high amount of read requests, the system may increase the size of the L2P cache at the expense of the write buffer (which may be decreased). Likewise, if the system notices a high amount of write requests, the system may increase the size of the L2P cache at the expense of the read buffer (which may be decreased).

公开(公告)号：US20210240608A1

公开(公告)日：2021-08-05

申请号：US17051995

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Greg A. Blodgett

IPC: G06F12/02 ,  G06F12/14 ,  G06F3/06

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A host logical-to-physical (L2P) table of the NAND device has an associated map. Entries in the map correspond to one or more logical addresses (LA) and indicate whether the host L2P table is current for those LAs. If the table is not current, then a request will bypass the host L2P table, using a standard device L2P lookup instead. Otherwise, the host L2P table can be used.

公开(公告)号：US20210157501A1

公开(公告)日：2021-05-27

申请号：US17164156

申请日：2021-02-01

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Sebastien Andre Jean ,  Jianmin Huang

IPC: G06F3/06 ,  G06F12/10

Abstract: Devices, methods, and machine-readable mediums are disclosed to create NAND-level logical partitions instead of physical partitions, for example, in a common pool of memory of a NAND memory device. A command can be received from a host to create a physical partition in a common pool of memory of the NAND memory device. A NAND-level logical partition can be created in the common pool of memory, instead of creating the physical partition, without allocating specific memory cells of the common pool of memory to the NAND-level logical partition. A response can be sent to the host indicative that the physical partition in the common pool of memory has been created, the response comprising a partition identifier and a range of Logical Block Addresses (LBAs) for the partition in the common pool of memory.

公开(公告)号：US10950310B2

公开(公告)日：2021-03-16

申请号：US16727472

申请日：2019-12-26

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Jianmin Huang ,  Preston Allen Thomson ,  Sebastien Andre Jean

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/11556

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US10824371B2

公开(公告)日：2020-11-03

申请号：US16012750

申请日：2018-06-19

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/04 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.

公开(公告)号：US20200327934A1

公开(公告)日：2020-10-15

申请号：US16915537

申请日：2020-06-29

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Ting Luo

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.

公开(公告)号：US10579288B2

公开(公告)日：2020-03-03

申请号：US15692299

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F21/00 ,  G06F3/06 ,  G06F12/02 ,  G06F21/79

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US10453543B2

公开(公告)日：2019-10-22

申请号：US15799577

申请日：2017-10-31

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G11C16/34 ,  G01R31/3193 ,  G11C29/52 ,  G11C29/44 ,  G11C29/56

Abstract: Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.

公开(公告)号：US10437734B2

公开(公告)日：2019-10-08

申请号：US15692622

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F12/1009

Abstract: Devices and techniques for memory constrained translation table management are disclosed herein. A level of a translation table is logically segmented into multiple segments. Here, a bottom level of the translation table includes a logical to physical address pairing for a portion of a storage device and other levels of the translation table include references within the translation table. The multiple segments are written to the storage device. A first segment of the multiple segments is loaded to byte-addressable memory. A request for an address translation is received and determined to be for an address referred to by a second segment of the multiple segments. The first segment is then replaced with the second segment in the byte-addressable memory and the request is fulfilled using the second segment to locate a lower level of the translation table that includes the address translation.