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    Memory address translation
    42.
    发明授权
    Memory address translation 有权

    公开(公告)号：US08756400B2

    公开(公告)日：2014-06-17

    申请号：US13859502

    申请日：2013-04-09

    Applicant: Micron Technology, Inc.

    Inventor： Troy A. Manning ,  Martin L. Culley ,  Troy D. Larsen

    IPC: G06F12/00

    Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

    Coherent memory access
    43.
    发明授权
    Coherent memory access 有权

    公开(公告)号：US11620228B2

    公开(公告)日：2023-04-04

    申请号：US17843387

    申请日：2022-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Timothy P. Finkbeiner ,  Troy D. Larsen

    IPC: G06F12/00 ,  G06F12/0877

    Abstract: Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address. Coherent access can be provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address.

    Modifiable repair solutions for a memory array
    44.
    发明授权
    Modifiable repair solutions for a memory array 有权

    公开(公告)号：US11430539B2

    公开(公告)日：2022-08-30

    申请号：US16914927

    申请日：2020-06-29

    Applicant: Micron Technology, Inc.

    Inventor： Troy A. Manning ,  Troy D. Larsen ,  Jonathan D. Harms ,  Glen E. Hush ,  Timothy P. Finkbeiner

    IPC: G11C29/44 ,  G11C29/42 ,  G11C29/00 ,  G11C29/18 ,  G11C29/24

    Abstract: Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.

    CONTENT ADDRESSABLE MEMORY (CAM) ADDRESSING
    47.
    发明申请
    CONTENT ADDRESSABLE MEMORY (CAM) ADDRESSING 有权

    公开(公告)号：US20210365383A1

    公开(公告)日：2021-11-25

    申请号：US17324250

    申请日：2021-05-19

    Applicant: Micron Technology, Inc.

    Inventor： Harold Robert G. Trout ,  Timothy P. Finkbeiner ,  Troy A. Manning ,  Glen E. Hush ,  Troy D. Larsen

    IPC: G06F12/10 ,  G11C15/04

    Abstract: Apparatuses, systems, and methods for mapping a virtual address using a CAM are described. A parallel structure of a CAM can enable functions of a MMU to be integrated into a single operation performed using the CAM such that a virtual address of a memory array can be mapped directly to a row of a memory. An example method includes receiving an access command and address information for a memory array; identifying a virtual address and a physical address of the memory array based on the received address information; comparing, during a time period associated with the access command, the virtual address and the physical address to virtual addresses and physical addresses, respectively, of the memory array stored in a CAM; and accessing, during the time period, a row of the memory array coupled to a row of the CAM storing the virtual address and the physical address.

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