公开(公告)号：US11538526B2

公开(公告)日：2022-12-27

申请号：US17162693

申请日：2021-01-29

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C11/22 ,  G11C14/00

Abstract: The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

公开(公告)号：US11527279B2

公开(公告)日：2022-12-13

申请号：US16908299

申请日：2020-06-22

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G06F11/30 ,  G11C11/22 ,  G06F11/07

Abstract: Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.

公开(公告)号：US20220319618A1

公开(公告)日：2022-10-06

申请号：US17415646

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Umberto Di Vincenzo ,  Ferdinando Bedeschi

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/22 ,  G11C29/52

Abstract: The present disclosure relates to a method for accessing an array of memory cells, including storing a set of user data in a plurality of memory cells, storing, in a portion of the array, additional information representative of a voltage difference between a first threshold voltage and a second threshold voltage of the memory cells programmed to a first logic state, applying to the array a read voltage to activate a first group of memory cells corresponding to a preset number of memory cells, determining that the first group of memory cells has been activated based on applying the read voltage, wherein the read voltage is equal to the first threshold voltage when the first group of memory cells has been activated, and based on the additional data information, applying the voltage difference to the array to activate a second group of memory cells programmed to the first logic state.

公开(公告)号：US11264074B2

公开(公告)日：2022-03-01

申请号：US17354672

申请日：2021-06-22

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/12 ,  G11C11/22 ,  G11C11/56 ,  G11C11/00

Abstract: Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

公开(公告)号：US11244739B2

公开(公告)日：2022-02-08

申请号：US16771659

申请日：2019-12-23

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/14 ,  G11C29/20 ,  G11C29/12

Abstract: Methods and apparatuses with counter-based reading are described.
In a memory device, a memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.

公开(公告)号：US20220020412A1

公开(公告)日：2022-01-20

申请号：US17362348

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Angelo Visconti

IPC: G11C11/22 ,  G11C7/06

Abstract: Methods, systems, and devices for read operations based on a dynamic reference are described. A memory device may include a set of memory cells each associated with a capacitive circuit including a first and second capacitor. After receiving a read command, the memory device may couple each capacitive circuit with a respective memory cell (e.g., to transfer a charge stored by each respective memory cell to a capacitive circuit) and may couple the second capacitor of each capacitive circuit to a reference voltage bus. Thus, a reference voltage on the reference voltage bus may be based on an average charge across the second capacitors of each capacitive circuit. The memory device may then compare a charge stored by the first and second capacitors of each capacitive circuit with the reference voltage bus and may output a set of values stored by the set of memory cells based on the comparing.

公开(公告)号：US20210343322A1

公开(公告)日：2021-11-04

申请号：US17323968

申请日：2021-05-18

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22

Abstract: Methods, systems, and devices for accessing a ferroelectric memory cell are described. In some examples, during a first portion of an access procedure, the voltages of a digit line and word line coupled with the memory cell may be increased while the voltage of a plate coupled with the memory cell is held constant, which may support sensing a logic state stored by the memory cell prior the access procedure, and which may result in a first logic state being written to the memory cell. A voltage of the plate may then be increased, and the digit line may then be coupled with the plate. Because the first logic state was previously written to the memory cell, a target logic state may not need to be subsequently written to the memory cell unless different than the first logic state.

公开(公告)号：US11145367B2

公开(公告)日：2021-10-12

申请号：US17174117

申请日：2021-02-11

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

IPC: G11C13/00 ,  G11C16/28 ,  G11C7/10 ,  G11C16/04

Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.

公开(公告)号：US11107519B2

公开(公告)日：2021-08-31

申请号：US16601427

申请日：2019-10-14

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Lucia Di Martino

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/22 ,  G11C7/02

Abstract: Techniques are described herein for mitigating parasitic signals induced by state transitions during an access operation of a selected memory cell in a memory device. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended coupling between various components of the memory device may occur during an access operation. To mitigate parasitic signals induced by the unintended coupling, the memory device may isolate the selected memory cell from a selected digit line during certain portions of the access operation. The memory device may isolate the selected memory cell when the plate transitions from a first voltage to a second, when the selected digit line transitions from a third voltage to a fourth voltage, or a combination thereof.

公开(公告)号：US11081204B1

公开(公告)日：2021-08-03

申请号：US16908303

申请日：2020-06-22

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/02 ,  G11C5/02 ,  G11C11/4074 ,  G11C11/4091

Abstract: Methods, systems, and devices for method for setting a reference voltage for read operations are described. A memory device may perform a first read operation on a set of memory cells using a first reference voltage and detect a first codeword based on performing the first read operation using the first reference voltage. The memory device may compare a first quantity of bits of the first codeword having a first logic value (e.g., a logic value ‘1’) with an expected quantity of bits having the first logic value (e.g., the expected quantity of logic value ‘1’s stored by the set of memory cells). The memory device may determine whether to perform a second read operation on the set of memory cells using a second reference voltage different than the first reference voltage (e.g., greater or less than the first reference voltage) based on the comparing.