公开(公告)号：US07494854B2

公开(公告)日：2009-02-24

申请号：US11768814

申请日：2007-06-26

申请人： Ming-Dou Ker ,  Che-Hao Chuang

发明人： Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L29/74 ,  H01L21/332

CPC分类号： H01L27/0266

摘要： A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

公开(公告)号：US20080297238A1

公开(公告)日：2008-12-04

申请号：US12022979

申请日：2008-01-30

申请人： Ming-Dou Ker ,  Jung-Sheng Chen ,  Chun-Yuan Hsu

发明人： Ming-Dou Ker ,  Jung-Sheng Chen ,  Chun-Yuan Hsu

IPC分类号： G05F1/10

CPC分类号： G05F3/242

摘要： A current source circuit is provided. The circuit includes a first transistor and at least one second transistor. A first source/drain terminal of the first transistor is coupled to a bias voltage. A second source/drain terminal of the first transistor is used to receive a current signal, and the second source/drain terminal of the first transistor is coupled to a gate terminal of the first transistor. A first source/drain terminal of the second transistor is grounded. A second source/drain terminal of the second transistor is coupled to a voltage source and outputs a bias current. A gate terminal of the second transistor is coupled to the gate terminal of the first transistor.

摘要翻译： 提供电流源电路。 该电路包括第一晶体管和至少一个第二晶体管。 第一晶体管的第一源极/漏极端子耦合到偏置电压。 第一晶体管的第二源极/漏极端子用于接收电流信号，并且第一晶体管的第二源极/漏极端子耦合到第一晶体管的栅极端子。 第二晶体管的第一源极/漏极端子接地。 第二晶体管的第二源极/漏极端子耦合到电压源并输出偏置电流。 第二晶体管的栅极端子耦合到第一晶体管的栅极端子。

公开(公告)号：US07439597B2

公开(公告)日：2008-10-21

申请号：US11618247

申请日：2006-12-29

申请人： Yu-Da Shiu ,  Chyh-Yih Chang ,  Ming-Dou Ker ,  Che-Hao Chuang

发明人： Yu-Da Shiu ,  Chyh-Yih Chang ,  Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L27/14

CPC分类号： H01L31/103 ,  H01L27/14609 ,  H01L31/105

摘要： An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

摘要翻译： 用于将入射光信号转换成电信号的集成电路装置包括半导体衬底，形成在半导体衬底内部的阱区，形成在阱区上的电介质层和用于接收入射光信号的多晶硅层，形成 包括p型部分，n型部分和设置在p型和n型部分之间的未掺杂部分，其中阱区被偏置以控制多晶硅层以提供电信号 。

公开(公告)号：US20080232013A1

公开(公告)日：2008-09-25

申请号：US12134061

申请日：2008-06-05

申请人： Ming-Dou Ker ,  Wen-Yi Chen ,  Che-Hao Chuang

发明人： Ming-Dou Ker ,  Wen-Yi Chen ,  Che-Hao Chuang

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

摘要翻译： 用于静电放电（ESD）保护的电路包括电阻器，与电阻器串联连接的电容器，包括栅极的第一晶体管，栅极连接到第一电源，通过电阻向栅极提供第一电压，第一 端子连接到第一电源，第二晶体管包括栅极，栅极连接到第二电源，第二电源提供小于第一电压的第二电压，第二晶体管具有连接到第二电源的第一端子 第一晶体管的端子和包括栅极的第三晶体管，栅极连接到第二电源，第三晶体管的第一端子连接到第二晶体管的第二端子，第二端子连接到第二晶体管， 参考电压不同于第一电压和第二电压。

公开(公告)号：US20080203424A1

公开(公告)日：2008-08-28

申请号：US12118364

申请日：2008-05-09

申请人： Zi-Ping Chen ,  Ming-Dou Ker

发明人： Zi-Ping Chen ,  Ming-Dou Ker

IPC分类号： H01L33/00 ,  H01L23/62

CPC分类号： H01L27/0255

摘要： A diode with low substrate current leakage and suitable for BiCMOS process technology. A buried layer is formed on a semiconductor substrate. A connection region and well contact the buried layer. Isolation regions are adjacent to two sides of the buried layer, each deeper than the buried layer. The isolation regions and the buried layer isolate the connection zone and the well from the substrate. The first doped region in the well is a first electrode. The well and the connection region are electrically connected, acting as a second electrode.

摘要翻译： 具有低衬底电流泄漏并适用于BiCMOS工艺技术的二极管。 在半导体衬底上形成掩埋层。 连接区域和阱接触埋层。 隔离区域与埋层的两侧相邻，每一个都比埋层更深。 隔离区域和掩埋层将连接区域和阱与衬底隔离。 阱中的第一掺杂区域是第一电极。 阱和连接区域电连接，用作第二电极。

公开(公告)号：US20080106835A1

公开(公告)日：2008-05-08

申请号：US11842177

申请日：2007-08-21

申请人： Ming-Dou Ker ,  Chih-Kang Deng

发明人： Ming-Dou Ker ,  Chih-Kang Deng

IPC分类号： H02H9/00

CPC分类号： G02F1/136204 ,  H01L27/0248

摘要： An active device array substrate includes pixel units, scan lines, data lines, electrostatic discharge (ESD) protection elements, a short ring and an ESD biased generator. Each pixel unit is electrically connected to the corresponding scan line and data line. Each ESD protection element has a first connection terminal, a second connection terminal and a third connection terminal, wherein the first connection terminal is electrically connected to one of the corresponding scan line and data line, the second connection terminal is electrically connected to the short ring, and the third connection terminal is electrically connected to the ESD biased generator. As an ESD stress occurs, the ESD biased generator provides a voltage to the ESD protection elements to turn on them. It causes that the accumulated electrostatic charges are conducted into the lowest potential of the substrate through the short rings, so as to prevent the pixel units from ESD damaging.

摘要翻译： 有源器件阵列衬底包括像素单元，扫描线，数据线，静电放电（ESD）保护元件，短环和ESD偏置发生器。 每个像素单元电连接到相应的扫描线和数据线。 每个ESD保护元件具有第一连接端子，第二连接端子和第三连接端子，其中第一连接端子电连接到相应的扫描线和数据线之一，第二连接端子电连接到短环 并且第三连接端子电连接到ESD偏置发生器。 当ESD应力发生时，ESD偏置发生器向ESD保护元件提供电压以接通它们。 这导致累积的静电电荷通过短环进入衬底的最低电位，以防止像素单元受到ESD损害。

公开(公告)号：US20070188952A1

公开(公告)日：2007-08-16

申请号：US11618674

申请日：2006-12-29

申请人： Ming-Dou Ker ,  Jang-Jie Peng ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Jang-Jie Peng ,  Hsin-Chin Jiang

IPC分类号： G01S13/08 ,  H02H9/00

CPC分类号： H01L27/0248 ,  H03K17/0822

摘要： An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.

摘要翻译： 一个片内闭锁保护电路。 上拉保护电路包括核心电路，电源开关和电流提取器。 电源开关控制流经核心电路的大电流。 当前提取器检测主电流的幅度。 电源开关，核心电路和电流提取器串联在相对较高的电力线和相对低的电力线之间。 当主电流超过预定幅度时，电源开关被关闭，导致闭锁停止。

公开(公告)号：US20070171587A1

公开(公告)日：2007-07-26

申请号：US11307168

申请日：2006-01-26

申请人： Chien-Ming Lee ,  Ming-Dou Ker

发明人： Chien-Ming Lee ,  Ming-Dou Ker

IPC分类号： H02H9/00

CPC分类号： H01L27/0285

摘要： The present invention provides ESD protection circuits. The circuit includes: a resistor, a capacitance, a first transistor, an inverter set, and a second transistor. The resistor is connected between a first voltage and node N1. The capacitor is connected between node N1 and a second voltage. The first transistor has a first terminal coupled to the first voltage, a second terminal coupled to the second voltage, and a third terminal coupled to node N2. The inverter set has an input terminal coupled to node N1 and an output terminal coupled to node N2. The second transistor has a first terminal coupled to a first inverter of the inverter set, a second terminal coupled to the second voltage, and a third terminal coupled to an output terminal of a second inverter of the inverter set. The output terminals of the first and the second inverters correspond to opposite logic levels.

摘要翻译： 本发明提供ESD保护电路。 该电路包括：电阻器，电容器，第一晶体管，反相器组和第二晶体管。 电阻连接在第一电压和节点N 1之间。 电容器连接在节点N1和第二电压之间。 第一晶体管具有耦合到第一电压的第一端子，耦合到第二电压的第二端子和耦合到节点N 2的第三端子。 逆变器组具有耦合到节点N1的输入端和耦合到节点N 2的输出端。 第二晶体管具有耦合到逆变器组的第一反相器的第一端子，耦合到第二电压的第二端子和耦合到逆变器组的第二反相器的输出端子的第三端子。 第一和第二反相器的输出端对应于相反的逻辑电平。

公开(公告)号：US07244992B2

公开(公告)日：2007-07-17

申请号：US10727550

申请日：2003-12-05

申请人： Ming-Dou Ker ,  Che-Hao Chuang

发明人： Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

摘要翻译： 一种适用于静电放电（ESD）保护电路的半导体器件，包括半导体衬底，在衬底中形成的第一阱，在衬底中形成的第二阱以及形成在第二阱中的第一掺杂区，其中， 第一阱，第二阱和第一掺杂区域共同形成寄生双极结型晶体管（BJT），其中第一阱是BJT的集电极，第二阱是BJT的基极，第一掺杂区域 是BJT的发射器。

公开(公告)号：US07205641B2

公开(公告)日：2007-04-17

申请号：US11017053

申请日：2004-12-21

申请人： Yu-Da Shiu ,  Chyh-Yih Chang ,  Ming-Dou Ker ,  Che-Hao Chuang

发明人： Yu-Da Shiu ,  Chyh-Yih Chang ,  Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L31/075

CPC分类号： H01L31/03529 ,  H01L27/0255 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14643 ,  H01L31/02019 ,  H01L31/105 ,  Y02E10/50

摘要： An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

摘要翻译： 用于将入射光信号转换成电信号的集成电路装置包括半导体衬底，形成在半导体衬底内部的阱区，形成在阱区上的电介质层和用于接收入射光信号的多晶硅层，形成 包括p型部分，n型部分和设置在p型和n型部分之间的未掺杂部分，其中阱区被偏置以控制多晶硅层以提供电信号 。