公开(公告)号：US07041601B1

公开(公告)日：2006-05-09

申请号：US10653103

申请日：2003-09-03

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L21/311

CPC classification number: H01L29/7842 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a MOSFET type semiconductor device includes forming a fin structure and a dummy gate structure over the fin structure. Sidewall spacers may be formed adjacent the dummy gate structure. The dummy gate structure may be later removed and replaced with a metal layer that is formed at a high temperature (e.g., 600°–700° C.). The cooling of the metal layer induces strain to the fin structure that affects the mobility of the double-gate MOSFET.

Abstract translation: 制造MOSFET型半导体器件的方法包括在鳍结构上形成翅片结构和虚拟栅极结构。 侧壁间隔件可以与伪栅极结构相邻地形成。 可以稍后去除虚拟栅极结构并用在高温（例如600℃-700℃）下形成的金属层代替。 金属层的冷却会引起对鳍结构的应变，从而影响双栅极MOSFET的迁移率。

公开(公告)号：US06958512B1

公开(公告)日：2005-10-25

申请号：US10770010

申请日：2004-02-03

Applicant: Yider Wu ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Yider Wu ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/788

CPC classification number: H01L29/42324 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7881

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, a conductive structure and a control gate. The insulating layer may be formed on the substrate and the fin may be formed on the insulating layer. The conductive structure may be formed near a side of the fin and the control gate may be formed over the fin. The conductive structure may act as a floating gate electrode for the non-volatile memory device.

Abstract translation: 非易失性存储器件包括衬底，绝缘层，鳍，导电结构和控制栅。 绝缘层可以形成在基板上，并且鳍可以形成在绝缘层上。 导电结构可以形成在鳍的一侧附近，并且控制栅可以形成在翅片上。 导电结构可以用作非易失性存储器件的浮栅电极。

公开(公告)号：US06933558B2

公开(公告)日：2005-08-23

申请号：US10726508

申请日：2003-12-04

Applicant: Wiley Eugene Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/785

Abstract: A memory device includes a conductive structure, a number of dielectric layers and a control gate. The dielectric layers are formed around the conductive structure and the control gate is formed over the dielectric layers. A portion of the conductive structure functions as a drain region for the memory device and at least one of the dielectric layers functions as a charge storage structure for the memory device. The dielectric layers may include oxide-nitride-oxide layers.

Abstract translation: 存储器件包括导电结构，多个电介质层和控制栅极。 电介质层形成在导电结构周围，并且控制栅极形成在电介质层上。 导电结构的一部分用作存储器件的漏极区，并且至少一个介电层用作存储器件的电荷存储结构。 电介质层可以包括氧化物 - 氮化物 - 氧化物层。

公开(公告)号：US06897527B2

公开(公告)日：2005-05-24

申请号：US10833112

申请日：2004-04-28

Applicant: Srikanteswara Dakshina-Murthy ,  Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

Inventor： Srikanteswara Dakshina-Murthy ,  Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L29/786 ,  H01L27/01

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

Abstract: A semiconductor device includes a fin and a layer formed on at least a portion of the fin. The fin includes a first crystalline material. The layer includes a second crystalline material, where the first crystalline material has a larger lattice constant than the second crystalline material to induce tensile strain within the layer.

Abstract translation: 半导体器件包括翅片和形成在鳍片的至少一部分上的层。 翅片包括第一结晶材料。 该层包括第二结晶材料，其中第一结晶材料具有比第二结晶材料更大的晶格常数以在层内引起拉伸应变。

公开(公告)号：US06893930B1

公开(公告)日：2005-05-17

申请号：US10161452

申请日：2002-05-31

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L29/66598 ,  H01L21/26513 ,  H01L29/665 ,  H01L29/6653

Abstract: For fabricating a field effect transistor on an active device area of a semiconductor substrate, a gate dielectric and a gate electrode are formed on the active device area of the semiconductor substrate. Antimony (Sb) dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form at least one of drain and source extension junctions and/or drain and source contact junctions. A low temperature thermal anneal process at a temperature less than about 950° Celsius is performed for activating the antimony (Sb) dopant within the drain and source extension junctions and/or drain and source contact junctions. In one embodiment of the present invention, the drain and source contact junctions are formed and thermally annealed before the formation of the drain and source extension junctions in a disposable spacer process for further minimizing heating of the drain and source extension junctions. In another embodiment of the present invention, the drain and source extension junctions and/or the drain and source contact junctions are formed to be amorphous before the thermal anneal process. In that case, a SPE (solid phase epitaxy) activation process in performed for activating the antimony (Sb) dopant within the amorphous drain and source extension junctions and/or the amorphous drain and source contact junctions at a temperature less than about 650° Celsius.

Abstract translation: 为了在半导体衬底的有源器件区域上制造场效应晶体管，在半导体衬底的有源器件区域上形成栅极电介质和栅电极。 将锑（Sb）掺杂剂注入到半导体衬底的有源器件区域的暴露区域中，以形成漏极和源极延伸结和/或漏极和源极接触结中的至少一个。 在低于约950℃的温度下进行低温热退火工艺，以激活漏极和源极延伸结和/或漏极和源极接触接点内的锑（Sb）掺杂剂。 在本发明的一个实施例中，在一次性间隔器工艺中形成漏极和源极延伸接头之前，形成漏极和源极接触接头并进行热退火，以进一步最小化漏极和源极延伸接点的加热。 在本发明的另一实施例中，在热退火工艺之前，将漏极和源极延伸接头和/或漏极和源极接触接点形成为非晶体。 在这种情况下，在低于约650℃的温度下，在非晶漏极和源极延伸结和/或非晶漏极和源极接触点内激活用于激活锑（Sb）掺杂剂的SPE（固相外延）激活过程 。

公开(公告)号：US06787406B1

公开(公告)日：2004-09-07

申请号：US10638334

申请日：2003-08-12

Applicant: Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2184

CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/66803 ,  Y10S438/944

Abstract: A method facilitates the doping of fins of a semiconductor device that includes a substrate. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.

Abstract translation: 一种方法有助于掺杂包括衬底的半导体器件的散热片。 该方法包括在基板上形成翅片结构，其中每个翅片结构都包括形成在翅片上的盖。 该方法还包括执行第一倾斜角度注入工艺以用n型杂质掺杂第一个翅片，并执行第二倾斜角度注入工艺，以使p型杂质掺杂第二个翅片。

公开(公告)号：US06762483B1

公开(公告)日：2004-07-13

申请号：US10348910

申请日：2003-01-23

Applicant: Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

Inventor： Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

IPC: H01L2906

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/78687

Abstract: A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.

Abstract translation: 一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。 该方法还包括在每个双盖的侧面上形成间隔物，并在双盖下方的第一半导体材料中形成双翅片。 该方法还包括使双翅片变薄以产生窄的双翅片。

公开(公告)号：US06756643B1

公开(公告)日：2004-06-29

申请号：US10459579

申请日：2003-06-12

Applicant: Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/785 ,  H01L21/3212 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681

Abstract: A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.

Abstract translation: FinFET型半导体器件包括翅片结构，其上形成相对薄的非晶硅层，然后形成未掺杂的多晶硅层。 半导体器件可以使用化学机械抛光（CMP）进行平面化，其中非晶硅层用作阻挡层以防止损坏鳍结构。

公开(公告)号：US06657276B1

公开(公告)日：2003-12-02

申请号：US10163925

申请日：2002-06-06

Applicant: Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

Inventor： Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

IPC: H01L2900

CPC classification number: H01L29/7842 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78654

Abstract: A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.

Abstract translation: 形成在半导体材料层中的浅沟槽隔离区。 浅沟槽隔离区域包括形成在半导体材料层中的沟槽，沟槽由侧壁和底部限定; 由高K材料形成的沟槽内的衬垫，衬垫符合沟槽的侧壁和底部; 以及由隔离材料制成并填充并符合高K衬里的填充部分。 还公开了形成浅沟槽隔离区域的方法。

公开(公告)号：US06645797B1

公开(公告)日：2003-11-11

申请号：US10310926

申请日：2002-12-06

Applicant: Matthew S. Buynoski ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Haihong Wang ,  Chih-Yuh Yang ,  Bin Yu

Inventor： Matthew S. Buynoski ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Haihong Wang ,  Chih-Yuh Yang ,  Bin Yu

IPC: H01L2184

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further includes etching the mask and carbon layer to form at least one structure, where the structure has a first width, reducing the width of the carbon layer in the at least one structure to a second width, depositing an oxide layer to surround the at least one structure, removing a portion of the oxide layer and the mask, removing the carbon layer to form an opening in a remaining portion of the oxide layer for each of the at least one structure, filling the at least one opening with conductive material, and removing the remaining portion of the oxide layer and a portion of the conductive layer to form the fin.

Abstract translation: 一种在半导体器件中形成翅片的方法，包括：衬底，形成在衬底上的绝缘层和形成在绝缘层上的导电层，包括在导电层上形成碳层，并在碳层上形成掩模 。 该方法还包括蚀刻掩模和碳层以形成至少一种结构，其中结构具有第一宽度，将至少一个结构中的碳层的宽度减小到第二宽度，沉积氧化物层以围绕 至少一个结构，去除所述氧化物层和所述掩模的一部分，除去所述碳层以在所述至少一个结构中的每一个结构的氧化物层的剩余部分中形成开口，用导电材料填充所述至少一个开口 并且去除氧化物层的剩余部分和导电层的一部分以形成翅片。