公开(公告)号：US5858863A

公开(公告)日：1999-01-12

申请号：US722944

申请日：1996-09-27

申请人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

发明人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

IPC分类号： B65G49/07 ,  B23Q41/00 ,  B23Q41/02 ,  C23C14/56 ,  C23C16/54 ,  G05B19/418 ,  H01L21/00 ,  H01L21/02 ,  H01L21/027 ,  H01L21/205 ,  H01L21/285 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/677 ,  H01L21/68

CPC分类号： C23C14/568 ,  C23C16/54 ,  G05B19/41865 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67276 ,  H01L21/67727 ,  H01L21/67745 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/28 ,  Y10S414/135 ,  Y10S414/137 ,  Y10S438/908 ,  Y10T29/41

摘要： Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system. Moreover, since the fabricating system including processing apparatuses is periodically controlled at a cycle time T min, the scheduling of a plurality of works can be made easy, to enhance the level of optimization, thus improving the productivity.

摘要翻译： 公开了一种制造系统，其包括通过机构间传送器彼此连接的多个处理装置，其中一组半导体晶片在处理装置中被处理，并且其他组的晶片被传送到指定的处理装置一段时间间隔 从（To + T）到一个时间To; 并且处理另一组晶片，并且剩余的晶片组从（To + T）到（To + 2T）的时间间隔被传输。 由于处理装置可以从时间间隔T min接收来自装置间运送装置的作品中的至少一个，因此在时间间隔T min内完成从运送装置到处理装置的作品的分配。 在每个时间间隔T min内运输运输车被清空，并且卸载到排空运输车，这使得在制造系统中运输多个作业的调度，控制和管理变得容易。 此外，由于包括处理装置的制造系统在周期时间T min周期性地进行控制，因此能够容易地进行多个作业的调度，提高优化等级，提高生产率。

公开(公告)号：US5695897A

公开(公告)日：1997-12-09

申请号：US564615

申请日：1995-11-29

申请人： Noriyuki Mitome ,  Eiichi Murakami ,  Shigeyuki Uzawa

发明人： Noriyuki Mitome ,  Eiichi Murakami ,  Shigeyuki Uzawa

IPC分类号： G03F7/20 ,  G03F9/00

CPC分类号： G03F9/7084 ,  G03F7/70458 ,  G03F9/7003

摘要： An alignment method or an exposure method in an exposure process in which a first stepper having a first reduction magnification and a second stepper having a second reduction magnification, higher than the first reduction magnification, are used in combination. For a global alignment through the first stepper on the basis of alignment marks having been defined through the second stepper in relation to shots thereof, in every shot of the first stepper the position of such alignment mark or marks to be measured is made variable with respect to the shot center.

摘要翻译： 组合使用具有第一缩小倍率的第一步进机和具有高于第一减速倍率的第二减速倍率的第二步进机的曝光处理中的对准方法或曝光方法。 对于通过第一步进机进行的全局对准，其基于已经通过第二步进器相对于其镜头定义的对准标记，在第一步进机的每次镜头中，使这样的对准标记或待测量的标记的位置相对于 到射击中心。

公开(公告)号：US5338942A

公开(公告)日：1994-08-16

申请号：US90

申请日：1993-01-04

申请人： Akio Nishida ,  Eiichi Murakami ,  Kiyokazu Nakagawa

发明人： Akio Nishida ,  Eiichi Murakami ,  Kiyokazu Nakagawa

IPC分类号： H01L21/20 ,  H01L21/203 ,  H01L21/331 ,  H01L21/338 ,  H01L29/06 ,  H01L29/165 ,  H01L29/267 ,  H01L29/73 ,  H01L29/737 ,  H01L29/778 ,  H01L29/812 ,  H01L29/04

CPC分类号： H01L29/267 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L29/0657 ,  H01L29/165

摘要： A semiconductor device comprising a semiconductor crystalline substrate having projections each thereof having an area of 0.01 .mu.m.sup.2 to 4 .mu.m.sup.2 or stripe projections each thereof having a width of 0.01 .mu.m to 1 .mu.m and semiconductor crystalline layers formed on the projections, each of the layers having lattice constants different from those of the semiconductor crystalline substrate preferably by 0.5% or more. The semiconductor device is free of dislocations and thermally stable. The semiconductor device can be fabricated by performing such processes as forming projections on the substrate and forming semiconductor crystalline layers on the projections by molecular beam epitaxy.

摘要翻译： 一种半导体器件，包括具有其面积为0.01μm至4μm的突起的半导体晶体基板或其宽度为0.01μm至1μm的条形突起，以及形成在所述突起上的半导体晶体层 这些层的晶格常数与半导体结晶基板的晶格常数不同，优选为0.5％以上。 半导体器件没有位错并且热稳定。 半导体器件可以通过进行诸如在衬底上形成突起并通过分子束外延在突起上形成半导体晶体层的工艺来制造。

公开(公告)号：US5241197A

公开(公告)日：1993-08-31

申请号：US759772

申请日：1991-09-13

申请人： Eiichi Murakami ,  Kiyokazu Nakagawa ,  Takashi Ohshima ,  Hiroyuki Eto ,  Masanobu Miyao

发明人： Eiichi Murakami ,  Kiyokazu Nakagawa ,  Takashi Ohshima ,  Hiroyuki Eto ,  Masanobu Miyao

IPC分类号： H01L27/085 ,  H01L29/165 ,  H01L29/737 ,  H01L29/778 ,  H01L29/80

CPC分类号： H01L29/7378 ,  H01L27/085 ,  H01L29/165 ,  H01L29/7373 ,  H01L29/7782 ,  H01L29/802

摘要： A transistor having a high carrier mobility and suited for a high-speed operation can be formed by utilizing a fact that the carrier mobility in a strained germanium layer is large. A strain control layer is provided beneath the germanium layer to impose a compressive strain on the germanium layer, and the composition of the strain control layer in a predetermined range is used to generate the compressive strain surely.

摘要翻译： 可以通过利用应变锗层中的载流子迁移率大的事实来形成具有高载流子迁移率且适于高速操作的晶体管。 在锗层下方设置应变控制层，以在锗层上施加压缩应变，并且使用预定范围内的应变控制层的组成以确定地产生压缩应变。

公开(公告)号：US4795911A

公开(公告)日：1989-01-03

申请号：US14033

申请日：1987-02-12

申请人： Michio Kohno ,  Eiichi Murakami ,  Akiyoshi Suzuki

发明人： Michio Kohno ,  Eiichi Murakami ,  Akiyoshi Suzuki

IPC分类号： G01N21/94 ,  G01N21/88

CPC分类号： G01N21/94

摘要： An apparatus usable with an object having a surface with a pattern, for examining the state of the surface, includes a projecting system for directing a light beam to the surface of the object, and a collecting system for collecting scattered light from the surface of the object. A projection of the optical axis of the collecting system onto the surface of the object extends in a direction different from a projection onto the surface of the object of a major portion of light diffracted from the pattern. A light-receiving unit receives the scattered light as collected by the collecting system and for producing an output corresponding to the state of the surface of the object.

摘要翻译： 可用于具有用于检查表面状态的具有图案的表面的物体的装置包括用于将光束引导到物体的表面的投影系统和用于从该物体的表面收集散射光的收集系统 目的。 将收集系统的光轴投射到物体表面上的方向不同于从图案衍射的大部分光的物体的表面上的投影。 光接收单元接收由收集系统收集的散射光并产生与物体表面的状态对应的输出。

公开(公告)号：US20120318069A1

公开(公告)日：2012-12-20

申请号：US13499947

申请日：2011-06-20

申请人： Eiichi Murakami

发明人： Eiichi Murakami

IPC分类号： G01F1/66

CPC分类号： G01F1/667 ,  G01F1/662

摘要： An ultrasonic flowmeter apparatus, which can be mounted on a conduit flowing a fluid whose flow rate is to be measured, has two housing halves coupled swingably about an axis. Free ends of the housing halves include a clamp mechanism for closing and locking the halves in position. The halves have formed therein grooves 1a and 2a, respectively, and a pair of ultrasonic wave transmission and reception elements are provided on an inner wall of the groove 1a. When the conduit is clamped between the grooves, the conduit is urged against the inner walls and deformed into a substantially square cross sectional configuration. An ultrasonic wave beam B is projected from one of the elements into a fluid passing through the conduit, the beam is reflected by an opposite surface of the conduit urged against the groove 2a, and the reflected beam is received by the other element.

摘要翻译： 超声波流量计装置可以安装在流过要测量流体的流体的导管上，具有围绕轴线可摆动地联接的两个壳体半部。 外壳半部的自由端包括用于将半部闭合并锁定就位的夹紧机构。 半部分别形成有槽1a，2a，在槽1a的内壁上设置一对超声波收发元件。 当导管夹紧在凹槽之间时，导管被推靠在内壁上并变形成基本正方形的横截面构型。 超声波波束B从元件中的一个突出到通过导管的流体中，该波束被导管的相对表面反射，并且反射的波束被另一个元件接收。

公开(公告)号：US08093723B2

公开(公告)日：2012-01-10

申请号：US13098648

申请日：2011-05-02

申请人： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

发明人： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

摘要翻译： 在具有多层埋地布线的半导体集成电路器件中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。

公开(公告)号：US07411301B2

公开(公告)日：2008-08-12

申请号：US11239371

申请日：2005-09-30

申请人： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

发明人： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

摘要翻译： 在具有多层埋地布线的半导体集成电路器件中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。

公开(公告)号：US07310563B2

公开(公告)日：2007-12-18

申请号：US11320778

申请日：2005-12-30

申请人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

发明人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

IPC分类号： G06F19/00

CPC分类号： C23C14/568 ,  C23C16/54 ,  G05B19/41865 ,  G05B2219/45031 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67276 ,  H01L21/67727 ,  H01L21/67745 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/28 ,  Y10S414/135 ,  Y10S414/137 ,  Y10S438/908 ,  Y10T29/41

摘要： A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.

摘要翻译： 一种用于系统的制造方法，包括通过机构间运送器彼此连接的多个处理装置。 半导体水在处理装置中进行处理，并以不同的时间间隔被传送到规定的处理装置，时间间隔设定为单位时间间隔的N倍。 由于制造系统包括以与单位时间相关的时间间隔周期性地控制的处理装置和装置间运输装置，所以与单位时间相关的间隔，可以有效地进行多个作业的调度以增强优化水平 ，从而提高生产率。

公开(公告)号：US20060111802A1

公开(公告)日：2006-05-25

申请号：US11320610

申请日：2005-12-30

申请人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

发明人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

IPC分类号： G06F19/00

CPC分类号： C23C14/568 ,  C23C16/54 ,  G05B19/41865 ,  G05B2219/45031 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67276 ,  H01L21/67727 ,  H01L21/67745 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/28 ,  Y10S414/135 ,  Y10S414/137 ,  Y10S438/908 ,  Y10T29/41

摘要： A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.