公开(公告)号：US20100131093A1

公开(公告)日：2010-05-27

申请号：US12556136

申请日：2009-09-09

Applicant: Natsuki YOKOYAMA ,  Yoshifumi KAWAMOTO ,  Eiichi MURAKAMI ,  Fumihiko UCHIDA ,  Kenichi MIZUISHI ,  Yoshio KAWAMURA

Inventor： Natsuki YOKOYAMA ,  Yoshifumi KAWAMOTO ,  Eiichi MURAKAMI ,  Fumihiko UCHIDA ,  Kenichi MIZUISHI ,  Yoshio KAWAMURA

IPC: G06F17/00

CPC classification number: C23C14/568 ,  C23C16/54 ,  G05B19/41865 ,  G05B2219/45031 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67276 ,  H01L21/67727 ,  H01L21/67745 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/28 ,  Y10S414/135 ,  Y10S414/137 ,  Y10S438/908

Abstract: A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.

Abstract translation: 一种系统的制造方法，其包括通过机器间运输机彼此连接的多个处理装置和存储管理半导体晶片的处理和传输信息的计算机。 处理装置具有用于装载和卸载容纳在载体中的多个半导体晶片的界面。 在处理装置的处理室中处理半导体水，并监视处理结果。 在处理中，在卸载包含在第二处理中处理的半导体晶片的第二载体之前，将包含在第一处理装置中处理的多个半导体晶片的第一载体通过装置间传送器传送到第二处理装置 装置，根据管理信息。

公开(公告)号：US20080243293A1

公开(公告)日：2008-10-02

申请号：US12153926

申请日：2008-05-28

Applicant: Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

Inventor： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

IPC: G06F17/00

CPC classification number: C23C14/568 ,  C23C16/54 ,  G05B19/41865 ,  G05B2219/45031 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67276 ,  H01L21/67727 ,  H01L21/67745 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/28 ,  Y10S414/135 ,  Y10S414/137 ,  Y10S438/908 ,  Y10T29/41

Abstract: A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.

公开(公告)号：US07392106B2

公开(公告)日：2008-06-24

申请号：US11320610

申请日：2005-12-30

Applicant: Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

Inventor： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

IPC: G06F19/00

CPC classification number: C23C14/568 ,  C23C16/54 ,  G05B19/41865 ,  G05B2219/45031 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67276 ,  H01L21/67727 ,  H01L21/67745 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/28 ,  Y10S414/135 ,  Y10S414/137 ,  Y10S438/908 ,  Y10T29/41

Abstract: A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.

Abstract translation: 一种系统的制造方法，其包括通过机器间运输机彼此连接的多个处理装置和存储管理半导体晶片的处理和传输信息的计算机。 处理装置具有用于装载和卸载容纳在载体中的多个半导体晶片的界面。 在处理装置的处理室中处理半导体水，并监视处理结果。 在处理中，在卸载包含在第二处理中处理的半导体晶片的第二载体之前，将包含在第一处理装置中处理的多个半导体晶片的第一载体通过装置间传送器输送到第二处理装置 装置，根据管理信息。

公开(公告)号：US06589871B2

公开(公告)日：2003-07-08

申请号：US09941757

申请日：2001-08-30

Applicant: Yoshio Kawamura ,  Souichi Katagiri ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

Inventor： Yoshio Kawamura ,  Souichi Katagiri ,  Kan Yasui ,  Masayuki Nagasawa ,  Ui Yamaguchi

IPC: H01L21302

CPC classification number: H01L22/20

Abstract: A processing method capable of presenting the processing condition with a high accuracy to improve the productivity, including a step of applying a first processing to a first substrate and a step of applying a second processing to the first substrate or the second processing to a second substrate and determining a correlation function for each of in-plane positions as the data for the difference in a plurality of processing steps to each of the in-plane positions in view of on the in-plain distribution data to the in-plane position of each of the substrate as a result of the plurality of processings, calculating the in-plain distribution characteristics of the substrate under a desired processing condition in view of the correlation function and processing the substrate based on the in-plain distribution characteristics.

Abstract translation: 一种处理方法，其能够高精度地呈现处理条件以提高生产率，包括对第一基板施加第一处理的步骤和对第一基板施加第二处理的步骤或第二处理的步骤 以及将每个平面内位置的相关函数确定为多个处理步骤中的差数据的数据，以便在每个平面内位置中考虑到不均匀分布数据到每个平面内位置的平面内位置 作为多个处理的结果，考虑到相关函数，在所需的处理条件下计算衬底的不均匀分布特性，并且基于平原分布特性来处理衬底。

公开(公告)号：US06524961B1

公开(公告)日：2003-02-25

申请号：US09359760

申请日：1999-07-22

Applicant: Souichi Katagiri ,  Kan Yasui ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato ,  Yoshio Kawamura ,  Shigeo Moriyama

Inventor： Souichi Katagiri ,  Kan Yasui ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato ,  Yoshio Kawamura ,  Shigeo Moriyama

IPC: H01L21461

CPC classification number: B24B37/245 ,  B24D3/32 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76819 ,  H01L21/7684

Abstract: A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.

公开(公告)号：US06099598A

公开(公告)日：2000-08-08

申请号：US106147

申请日：1998-06-29

Applicant: Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

Inventor： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

IPC: B65G49/07 ,  B23Q41/00 ,  B23Q41/02 ,  C23C14/56 ,  C23C16/54 ,  G05B19/418 ,  H01L21/00 ,  H01L21/02 ,  H01L21/027 ,  H01L21/205 ,  H01L21/285 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/677 ,  H01L21/68 ,  C23C14/00

CPC classification number: C23C14/568 ,  C23C16/54 ,  G05B19/41865 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67276 ,  H01L21/67727 ,  H01L21/67745 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/28 ,  Y10S414/135 ,  Y10S414/137 ,  Y10S438/908 ,  Y10T29/41

Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system. Moreover, since the fabricating system including processing apparatuses is periodically controlled at a cycle time T min, the scheduling of a plurality of works can be made easy, to enhance the level of optimization, thus improving the productivity.

Abstract translation: 公开了一种制造系统，其包括通过机构间传送器彼此连接的多个处理装置，其中一组半导体晶片在处理装置中被处理，并且其他组的晶片被传送到指定的处理装置一段时间间隔 从（To + T）到一个时间To; 并且处理另一组晶片，并且剩余的晶片组从（To + T）到（To + 2T）的时间间隔被传输。 由于处理装置可以从时间间隔T min接收来自装置间运送装置的作品中的至少一个，因此在时间间隔T min内完成从运送装置到处理装置的作品的分配。 在每个时间间隔T min内运输运输车被清空，并且卸载到排空运输车，这使得在制造系统中运输多个作业的调度，控制和管理变得容易。 此外，由于包括处理装置的制造系统在周期时间T min周期性地进行控制，因此能够容易地进行多个作业的调度，提高优化等级，提高生产率。

公开(公告)号：US5609511A

公开(公告)日：1997-03-11

申请号：US421247

申请日：1995-04-13

Applicant: Shigeo Moriyama ,  Yoshio Kawamura ,  Yoshio Homma ,  Kikuo Kusukawa ,  Takeshi Furusawa

Inventor： Shigeo Moriyama ,  Yoshio Kawamura ,  Yoshio Homma ,  Kikuo Kusukawa ,  Takeshi Furusawa

IPC: B23Q17/24 ,  B24B49/04 ,  B24B49/12 ,  B24D7/12 ,  H01L21/304 ,  B24B49/00 ,  B24B51/00

CPC classification number: B24B37/013 ,  B24B49/12 ,  B24D7/12

Abstract: Disclosed is a method of polishing a thin film layer to be polished, which is formed on the surface of a substrate, by pressing the substrate on the surface of a polishing pad and relatively moving the substrate and the polishing pad, the method comprising the steps of: detecting the position of a front surface of the thin film layer to be polished using a first sensor and also detecting the position of a bottom surface of the thin film layer using a second sensor, on the way of the polishing; calculating the residual thickness of the thin film layer on the basis of the detected positions of the front and bottom surfaces of the thin film layer; and controlling the processing condition of the subsequent polishing on the basis of the calculated residual thickness of the thin film layer.

Abstract translation: 本发明公开了一种通过将基板压在抛光垫的表面上并使基板和抛光垫相对移动而形成在基板表面上的抛光薄膜层的方法，该方法包括步骤 使用第一传感器检测待研磨的薄膜层的前表面的位置，并且在抛光的同时使用第二传感器检测薄膜层的底面的位置; 基于检测到的薄膜层的前表面和底表面的位置计算薄膜层的剩余厚度; 并根据计算出的薄膜层的残留厚度来控制后续研磨的处理条件。

公开(公告)号：US5601686A

公开(公告)日：1997-02-11

申请号：US642510

申请日：1996-05-03

Applicant: Yoshio Kawamura ,  Yoshifumi Kawamoto ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Natsuki Yokoyama ,  Eiichi Murakami ,  Yoshinori Nakayama ,  Eiichi Seya

Inventor： Yoshio Kawamura ,  Yoshifumi Kawamoto ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Natsuki Yokoyama ,  Eiichi Murakami ,  Yoshinori Nakayama ,  Eiichi Seya

IPC: B65G49/00 ,  B65G49/07 ,  H01L21/00 ,  H01L21/02 ,  H01L21/027 ,  H01L21/677

CPC classification number: H01L21/67748 ,  H01L21/67167 ,  H01L21/6719 ,  H01L21/67196 ,  H01L21/67742 ,  Y10S414/135 ,  Y10S414/139 ,  Y10S438/935

Abstract: A wafer transport method including the steps of preparing a semiconductor process equipment having a transport chamber, a process chamber, an interface means for connecting the transport chamber to the process chamber, and a transport means for transporting a semiconductor wafer from the transport chamber to the process chamber by way of the interface means; inserting the transport means mounting a substrate in a communicating corridor including a supply means and an exhaust means; and transporting the substrate while performing the supply and exhaust by sequentially controlling a supply shutoff means, an exhaust shutoff means, and a communicating shutoff means according to the position of a conductance part formed of a gap between the transport means and the communicating corridor. With this method, the substrate is transported at a high throughput without the contamination on the substrate while keeping the different atmospheric conditions of the transport chamber and the process chamber, thereby manufacturing a semiconductor device with a high performance.

Abstract translation: 一种晶片输送方法，包括以下步骤：制备具有输送室的半导体工艺设备，处理室，用于将输送室连接到处理室的接口装置，以及用于将半导体晶片从输送室输送到 处理室; 将安装基板的输送装置插入包括供给装置和排气装置的通信走廊中; 并且通过根据由传送装置和通信走廊之间的间隙形成的电导部分的位置顺序地控制供给关闭装置，排气关闭装置和连通关闭装置，在执行供应和排出的同时运送基板。 利用该方法，在保持输送室和处理室的不同大气条件的同时，以高通量输送基板而不会在基板上产生污染，从而制造具有高性能的半导体器件。

公开(公告)号：US5183744A

公开(公告)日：1993-02-02

申请号：US425028

申请日：1989-10-23

Applicant: Yoshio Kawamura ,  Shinji Tanaka ,  Kazuo Sato ,  Kenko Uchida ,  Hiroyuki Kohida

Inventor： Yoshio Kawamura ,  Shinji Tanaka ,  Kazuo Sato ,  Kenko Uchida ,  Hiroyuki Kohida

IPC: C12M1/32 ,  C12M3/00 ,  C12N13/00 ,  C12Q1/24

CPC classification number: C12Q1/24 ,  C12M35/02 ,  C12N13/00

Abstract: A method and an apparatus for the treatment of particles or biological cells are disclosed, wherein the particles or cells are precipitated or ascended depending on the specific gravity of a liquid used, and the particles or cells are handled with the aid of a holding plate. A method and an apparatus for the fusion of particles or cells are also disclosed, wherein an electric voltage is loaded on a position between electrodes in a microchamber to fuse the particles or cells held in the microchamber.

Abstract translation: 公开了一种用于处理颗粒或生物细胞的方法和装置，其中所述颗粒或细胞根据所用液体的比重而沉淀或上升，并且借助于保持板处理颗粒或细胞。 还公开了一种用于熔化颗粒或细胞的方法和装置，其中电压被加载在微室中的电极之间的位置，以熔化保持在微室中的颗粒或细胞。

公开(公告)号：US4584766A

公开(公告)日：1986-04-29

申请号：US542256

申请日：1983-10-14

Applicant: Shingo Ogawa ,  Hitoshi Miyahira ,  Kensaku Sato ,  Yoshio Kawamura ,  Hirosi Kaida ,  Yoshizi Itoh

Inventor： Shingo Ogawa ,  Hitoshi Miyahira ,  Kensaku Sato ,  Yoshio Kawamura ,  Hirosi Kaida ,  Yoshizi Itoh

IPC: H01R43/01 ,  H01R43/28 ,  B23P19/00

CPC classification number: H01R43/28 ,  H01R43/01 ,  Y10T29/49764 ,  Y10T29/53243

Abstract: Firstly, each of the cores of a multicore cable are connected at one end thereof to the respective contacts of one of two connectors at random. Then, using a detector for detecting the change of electrical conditions of the cores, detection is made in a random fashion for the other ends of the cores to determine to which line contact of the one connector the one end of the corresponding core has been connected. The other end of the detected core is connected to a contact of a desired line of the other connector. In this manner, the both ends of the cores are connected to contacts of desired lines of the two connectors.

Abstract translation: 首先，多芯电缆的每个芯在其一端连接到两个连接器之一的相应触点随机连接。 然后，使用用于检测芯的电气条件变化的检测器，以核心的另一端的随机方式进行检测，以确定相应核心的一端已经连接到一个连接器的哪个线路接触 。 检测到的核心的另一端连接到另一个连接器的所需线路的触点。 以这种方式，芯的两端连接到两个连接器的所需线的触点。