公开(公告)号：US08707278B2

公开(公告)日：2014-04-22

申请号：US13251463

申请日：2011-10-03

申请人： Gogul Balakrishnan ,  Naoto Maeda ,  Franjo Ivancic ,  Nishant Sinha ,  Aarti Gupta ,  Jing Yang

发明人： Gogul Balakrishnan ,  Naoto Maeda ,  Franjo Ivancic ,  Nishant Sinha ,  Aarti Gupta ,  Jing Yang

IPC分类号： G06F9/45

CPC分类号： G06F8/4434 ,  G06F8/24 ,  G06F8/443 ,  G06F8/51 ,  G06F8/75

摘要： A model is provided for transforming a program with a priori given class hierarchy that is induced by inheritance. An inheritance remover is configured to remove inheritance from a given program to produce an analysis-friendly program which does not include virtual-function pointer tables and runtime libraries associated with inheritance-related operations. The analysis-friendly program preserves the semantics of the given program with respect to a given class hierarchy. A clarifier is configured to identify implicit expressions and function calls and transform the given program into at least one intermediate program having explicit expressions and function calls.

摘要翻译： 提供了一个模型，用于使用由继承引发的先验给定的类层次结构来转换程序。 继承去除器配置为从给定的程序中删除继承，以生成一个不包含与继承相关的操作相关联的虚拟函数指针表和运行时库的分析友好的程序。 分析友好的程序保留给定程序相对于给定类层次结构的语义。 澄清器被配置为识别隐式表达式和函数调用，并将给定程序转换成具有显式表达式和函数调用的至少一个中间程序。

公开(公告)号：US08592254B2

公开(公告)日：2013-11-26

申请号：US13612337

申请日：2012-09-12

申请人： Joseph T. Lindgren ,  Warren M. Farnworth ,  William M. Hiatt ,  Nishant Sinha

发明人： Joseph T. Lindgren ,  Warren M. Farnworth ,  William M. Hiatt ,  Nishant Sinha

IPC分类号： H01L21/44

CPC分类号： H01L23/367 ,  H01L23/427 ,  H01L24/31 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/19041 ,  H01L2224/0401

摘要： Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.

摘要翻译： 本文公开了具有改善的散热的微电子器件，制造微电子器件的方法以及冷却微电子器件的方法。 在一个实施例中，微电子器件包括具有第一表面，与第一表面相对的第二表面的微电子衬底以及至少靠近第一表面的多个有源器件。 第二表面具有增加第二表面的表面积的多个传热表面特征。 在另一个实施例中，具有散热器和单相或多相热导体的外壳可以邻近第二表面定位以传递来自有源器件的热量。

公开(公告)号：US08508997B2

公开(公告)日：2013-08-13

申请号：US12646847

申请日：2009-12-23

申请人： Sanh D. Tang ,  Nishant Sinha ,  John Zahurak

发明人： Sanh D. Tang ,  Nishant Sinha ,  John Zahurak

IPC分类号： G11C11/34

CPC分类号： H01L27/11551 ,  G11C16/0458 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

摘要： Embodiments of the invention pertain to vertical memory structures. Embodiments of the invention describe memory nodes comprising two memory cells on opposing sides of a vertical channel separating a source region and a drain region. Embodiments of the invention may utilize floating gate NAND memory cells, polysilicon diodes, MiM diodes, or MiiM diodes. Embodiments of the invention may be used to form flash memory, RRAM, Memristor RAM, Oxide Ram or OTPROM.

摘要翻译： 本发明的实施例涉及垂直存储器结构。 本发明的实施例描述了在分离源区和漏区的垂直沟道的相对侧上包括两个存储单元的存储器节点。 本发明的实施例可以利用浮动栅极NAND存储器单元，多晶硅二极管，MiM二极管或者MiiM二极管。 本发明的实施例可用于形成闪速存储器，RRAM，忆阻器RAM，氧化物Ram或OTPROM。

公开(公告)号：US08431184B2

公开(公告)日：2013-04-30

申请号：US13103050

申请日：2011-05-07

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： B05D5/12

CPC分类号： H01L21/76877 ,  C25D5/02 ,  C25D5/04 ,  C25D5/08 ,  C25D5/10 ,  C25D21/10 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76879

摘要： Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings.

摘要翻译： 一些实施例包括在高纵横比开口和低纵横比开口内形成导电材料的方法。 首先，高纵横比开口可以填充第一导电材料，而低纵横比开口仅部分地填充有第一导电材料。 然后可以在高纵横比开口内相对于第一导电材料，在低纵横比开口内的第一导电材料上选择性地镀覆附加材料。 在一些实施例中，附加材料可以是仅部分填充低纵横比开口的活化材料，并且可以随后将另一种导电材料电镀到活化材料上以填充低纵横比开口。

公开(公告)号：US20120117547A1

公开(公告)日：2012-05-10

申请号：US13251463

申请日：2011-10-03

申请人： GOGUL BALAKRISHNAN ,  Naoto Maeda ,  Franjo Ivancic ,  Nishant Sinha ,  Aarti Gupta ,  Jing Yang

发明人： GOGUL BALAKRISHNAN ,  Naoto Maeda ,  Franjo Ivancic ,  Nishant Sinha ,  Aarti Gupta ,  Jing Yang

IPC分类号： G06F9/45

CPC分类号： G06F8/4434 ,  G06F8/24 ,  G06F8/443 ,  G06F8/51 ,  G06F8/75

摘要： A model is provided for transforming a program with a priori given class hierarchy that is induced by inheritance. An inheritance remover is configured to remove inheritance from a given program to produce an analysis-friendly program which does not include virtual-function pointer tables and runtime libraries associated with inheritance-related operations. The analysis-friendly program preserves the semantics of the given program with respect to a given class hierarchy. A clarifier is configured to identify implicit expressions and function calls and transform the given program into at least one intermediate program having explicit expressions and function calls.

摘要翻译： 提供了一个模型，用于使用由继承引发的先验给定的类层次结构来转换程序。 继承去除器配置为从给定的程序中删除继承，以生成一个不包含与继承相关的操作相关联的虚拟函数指针表和运行时库的分析友好的程序。 分析友好的程序保留给定程序相对于给定类层次结构的语义。 澄清器被配置为识别隐式表达式和函数调用，并将给定程序转换成具有显式表达式和函数调用的至少一个中间程序。

公开(公告)号：US20110078511A1

公开(公告)日：2011-03-31

申请号：US12894710

申请日：2010-09-30

申请人： Nishant Sinha ,  Chao Wang

发明人： Nishant Sinha ,  Chao Wang

IPC分类号： G06F11/08 ,  G06F11/00

CPC分类号： G06F11/3604

摘要： Methods and systems for concurrent program verification. A concurrent program is summarized into a symbolic interference skeleton (IS) using data flow analysis. Sequential consistency constraints are enforced on read and write events in the IS. Error conditions are checked together with the IS using a processor.

摘要翻译： 并发程序验证的方法和系统。 使用数据流分析将并发程序总结为符号干扰骨架（IS）。 在IS中的读写事件上执行顺序一致性约束。 使用处理器与IS一起检查错误状况。

公开(公告)号：US20100025854A1

公开(公告)日：2010-02-04

申请号：US12185675

申请日：2008-08-04

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L28/40 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76882 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.

摘要翻译： 本文公开了用于从微电子衬底去除导电材料（例如贵金属）的抛光系统和方法。 所述方法的若干实施例包括在基底材料中形成孔，将导电材料设置在基底材料和孔中，并将填充材料设置在导电材料上。 填充材料至少部分地填充孔。 然后抛光衬底材料以去除导电材料和孔的外部的填充材料的至少一部分，在此期间，填充材料在抛光衬底材料期间基本上防止导电材料污染到孔中。

公开(公告)号：US20090275208A1

公开(公告)日：2009-11-05

申请号：US12114174

申请日：2008-05-02

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： H01L21/306 ,  C23F1/12

CPC分类号： H01L21/3081 ,  H01L21/31111

摘要： Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.

摘要翻译： 一些实施方案包括去除其中二氧化硅暴露于包括活性氢和至少一种伯，仲，叔或季铵卤化物的混合物的二氧化硅的方法。 混合物还可以包括铊，BX 3和PQ 3中的一种或多种，​​其中X和Q是卤化物。 一些实施方案包括相对于掺杂二氧化硅选择性地蚀刻未掺杂二氧化硅的方法，其中在蚀刻之前将铊掺入掺杂的二氧化硅中。 一些实施方案包括含有掺杂铊的二氧化硅至约1重量％至约10重量％的浓度的物质的组合物。

公开(公告)号：US07608904B2

公开(公告)日：2009-10-27

申请号：US11717294

申请日：2007-03-12

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： H01L29/78 ,  H01L29/47

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device component includes at least one conductive via. The at least one conductive via may include a seed layer for facilitating adhesion of a conductive material within the via aperture, a barrier material and solder, or a silicon-containing filler. Systems including such semiconductor device components are also disclosed.

摘要翻译： 半导体器件部件包括至少一个导电通孔。 至少一个导电通孔可以包括种子层，用于促进导电材料在通孔孔内的粘附，阻挡材料和焊料，或含硅填料。 还公开了包括这种半导体器件部件的系统。

公开(公告)号：US07345350B2

公开(公告)日：2008-03-18

申请号：US10668914

申请日：2003-09-23

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： H01L31/00 ,  H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L31/108

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a conductive via in a semiconductor component is disclosed. The method includes providing a substrate having a first surface and an opposing, second surface. At least one hole is formed in the substrate extending between the first surface and the opposing, second surface. A seed layer is formed on a sidewall defining the at least one hole of the substrate and coated with a conductive layer, and a conductive or nonconductive filler material is introduced into the remaining space within the at least one hole. A method of forming a conductive via through a substrate using a blind hole is also disclosed. Semiconductor components and electronic systems having substrates including the conductive via of the present invention are also disclosed.

摘要翻译： 公开了一种在半导体部件中形成导电通孔的方法。 该方法包括提供具有第一表面和相对的第二表面的基底。 在基板上形成至少一个孔，该孔在第一表面和相对的第二表面之间延伸。 种子层形成在限定基底的至少一个孔并且涂覆有导电层的侧壁上，并且导电或非导电填充材料被引入至少一个孔内的剩余空间中。 还公开了使用盲孔通过基板形成导电通孔的方法。 还公开了具有包括本发明的导电通孔的基板的半导体元件和电子系统。