Compact In-Pixel High Dynamic Range Imaging
    41.
    发明申请
    Compact In-Pixel High Dynamic Range Imaging 有权
    紧凑像素高动态范围成像

    公开(公告)号:US20140103189A1

    公开(公告)日:2014-04-17

    申请号:US13651092

    申请日:2012-10-12

    CPC classification number: H01L27/14612 H04N5/3559

    Abstract: Embodiments of the invention describe providing a compact solution to provide high dynamic range imaging (HDRI or simply HDR) for an imaging pixel by utilizing a control node for resetting a floating diffusion node to a reference voltage value and for selectively transferring an image charge from a photosensitive element to a readout node. Embodiments of the invention further describe control node to have to a plurality of different capacitance regions to selectively increase the overall capacitance of the floating diffusion node. This variable capacitance of the floating diffusion node increases the dynamic range of the imaging pixel, thereby providing HDR for the host imaging system, as well as increasing the signal-to-noise ratio (SNR) of the imaging system.

    Abstract translation: 本发明的实施例描述了提供一种紧凑的解决方案,以通过利用用于将浮动扩散节点复位到参考电压值的控制节点和用于选择性地传输图像电荷的方法来为成像像素提供高动态范围成像(HDRI或简单的HDR) 感光元件到读出节点。 本发明的实施例进一步描述了控制节点必须具有多个不同的电容区域以选择性地增加浮动扩散节点的整体电容。 浮动扩散节点的这种可变电容增加了成像像素的动态范围,从而为主机成像系统提供了HDR,并且提高了成像系统的信噪比(SNR)。

    DUAL-FACING CAMERA ASSEMBLY
    42.
    发明申请

    公开(公告)号:US20130285183A1

    公开(公告)日:2013-10-31

    申请号:US13927495

    申请日:2013-06-26

    Abstract: Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate).In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.

    Uniform threshold voltage non-planar transistors

    公开(公告)号:US12154919B2

    公开(公告)日:2024-11-26

    申请号:US17326103

    申请日:2021-05-20

    Inventor: Hui Zang Gang Chen

    Abstract: Transistors having nonplanar electron channels in the channel width plane have one or more features that cause the different parts of the nonplanar electron channel to turn on at substantially the same threshold voltage. Advantageously, such transistors have substantially uniform threshold voltage across the nonplanar electron channel. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

    Flare-suppressing image sensor
    44.
    发明授权

    公开(公告)号:US11860383B2

    公开(公告)日:2024-01-02

    申请号:US17392023

    申请日:2021-08-02

    CPC classification number: G02B3/0043 H04N25/61 H04N25/70

    Abstract: Embodiments disclosed herein reduce petal flare. A flare-suppressing image sensor includes a plurality of pixels including a first set of pixels and a second set of pixels. The flare-suppressing image sensor further includes plurality of microlenses, where each microlens is aligned to a respective one of the first set of pixels. The flare-suppressing image sensor further includes plurality of sub-microlens, where each microlens array is aligned to a respective one of the second set of pixels.

    DUAL DEPTH JUNCTION STRUCTURES AND PROCESS METHODS

    公开(公告)号:US20230307474A1

    公开(公告)日:2023-09-28

    申请号:US17700858

    申请日:2022-03-22

    Inventor: Hui Zang Gang Chen

    CPC classification number: H01L27/14614 H01L27/14643 H01L27/14689

    Abstract: Transistors, electronic devices, and methods are provided. Transistors include a gate trench formed in a semiconductor substrate and extending to a gate trench depth, and a source and a drain formed as doped regions in the semiconductor substrate and having a first conductive type. The source and the drain are formed along a channel length direction of the transistor at a first end and a second end of the gate trench, respectively, and the source and the drain each includes a first doped region and a second doped region extending away from the first doped region. The second doped region extends to a depth in the semiconductor substrate deeper than the first doped region relative to a surface of the semiconductor substrate.

    Image sensor with through silicon fin transfer gate

    公开(公告)号:US11658198B2

    公开(公告)日:2023-05-23

    申请号:US16998783

    申请日:2020-08-20

    Inventor: Qin Wang Gang Chen

    CPC classification number: H01L27/14643 H01L27/14603 H01L27/14609

    Abstract: A device includes a photodiode, a floating diffusion region, a transfer gate, and a channel region. The photodiode is disposed in a semiconductor material. The photodiode is coupled to generate charge in response to incident light. The floating diffusion region is disposed in the semiconductor material. The transfer gate is disposed between the photodiode and the floating diffusion region. The channel region associated with the transfer gate is in the semiconductor material proximate to the transfer gate. The transfer gate is coupled to transfer the charge from the photodiode to the floating diffusion region through the channel region in response to a transfer signal coupled to be received by the transfer gate. The transfer gate includes a plurality of fin structures that extend into the semiconductor material and the photodiode.

    PYRAMID-SHAPED TRANSISTORS
    47.
    发明申请

    公开(公告)号:US20220376068A1

    公开(公告)日:2022-11-24

    申请号:US17326095

    申请日:2021-05-20

    Inventor: Hui Zang Gang Chen

    Abstract: Transistors include a pyramid-shaped gate trench defined by a triangular shape or a trapezoidal shape in a channel width plane and a trapezoidal shape in a channel length plane. Side wall portions of the pyramid-shaped gate trench form a channel having a triangular shape or a trapezoidal shape in the channel width plane. Advantageously, such transistors increase transconductance without increasing pixel width. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

    UNIFORM THRESHOLD VOLTAGE NON-PLANAR TRANSISTORS

    公开(公告)号:US20220375977A1

    公开(公告)日:2022-11-24

    申请号:US17326103

    申请日:2021-05-20

    Inventor: Hui Zang Gang Chen

    Abstract: Transistors having nonplanar electron channels in the channel width plane have one or more features that cause the different parts of the nonplanar electron channel to turn on at substantially the same threshold voltage. Advantageously, such transistors have substantially uniform threshold voltage across the nonplanar electron channel. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

    Pixel, associated image sensor, and method

    公开(公告)号:US11282886B2

    公开(公告)日:2022-03-22

    申请号:US16711239

    申请日:2019-12-11

    Inventor: Hui Zang Gang Chen

    Abstract: A pixel includes a semiconductor substrate, an upper surface thereof forming a trench having a trench depth relative to a planar region of the upper surface surrounding the trench, and in a plane perpendicular to the planar region; an upper width between the planar region and an upper depth that is less than the trench depth; and a lower width, between the upper depth and the trench depth, that is less than the upper width. A floating diffusion region adjacent to the trench extends away from the planar region to a junction depth exceeding the upper depth and is less than the trench depth. The photodiode region in the substrate includes a lower photodiode section beneath the trench and an upper photodiode section adjacent to the trench, beginning at a photodiode depth that is less than the trench depth, extending toward and adjoining the lower photodiode section.

    CELL DEEP TRENCH ISOLATION STRUCTURE FOR NEAR INFRARED IMPROVEMENT

    公开(公告)号:US20220020790A1

    公开(公告)日:2022-01-20

    申请号:US16931229

    申请日:2020-07-16

    Abstract: A pixel cell includes a photodiode disposed in a pixel cell region and proximate to a front side of a semiconductor layer to generate image charge in response to incident light directed through a backside to the photodiode. A cell deep trench isolation (CDTI) structure is disposed in the pixel cell region along an optical path of the incident light to the photodiode and proximate to the backside. The CDTI structure includes a central portion extending a first depth from the backside towards the front side. Planar outer portions extend laterally outward from the central portion. The planar output portions further extend a second depth from the backside towards the front side. The first depth is greater than the second depth. Planes formed by each of the planar outer portions intersect in a line coincident with a longitudinal center line of the central portion of the CDTI structure.

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