公开(公告)号：US5349544A

公开(公告)日：1994-09-20

申请号：US207317

申请日：1988-06-15

申请人： Michael J. Wright ,  Om P. Agrawal

发明人： Michael J. Wright ,  Om P. Agrawal

IPC分类号： H03K19/177 ,  H03L7/06 ,  H03L7/183 ,  G06J1/00

CPC分类号： H03L7/183

摘要： A PLL is integrated on the same chip as a programmable logic circuit and interconnected therewith in any of several useful ways. In one aspect of the invention, the output frequency of the PLL may be connected to the clock input of registers in the programmable logic circuit. If the PLL performs frequency multiplication, the chip then becomes a high-speed state machine synchronized to a lower-frequency input clock. In another aspect of the invention, the signal present at different parts of the phase lock loop may be provided to inputs of the programmable logic circuit. In another aspect, outputs of the programmable logic circuit may be used to control the operation and/or characteristics of various components in the PLL. For example, if a counter is included in the phase lock loop for causing the loop to generate a frequency multiple of the input signal, the counter may be made programmable according to outputs of the state machine. Similarly, the characteristics of the phase detector or loop filter may be dynamically adjusted according to outputs of the state machine. In yet another aspect of the invention, an output of the programmable logic circuit is, or is used to generate, one of the inputs to the phase detector in the PLL.

摘要翻译： PLL与可编程逻辑电路集成在同一个芯片上，并以几种有用的方式进行互连。 在本发明的一个方面，PLL的输出频率可以连接到可编程逻辑电路中的寄存器的时钟输入。 如果PLL执行倍频，芯片就成为与低频输入时钟同步的高速状态机。 在本发明的另一方面，存在于锁相环的不同部分的信号可以被提供给可编程逻辑电路的输入端。 在另一方面，可编程逻辑电路的输出可用于控制PLL中的各种组件的操作和/或特性。 例如，如果在锁相环中包括计数器以使环路产生输入信号的频率倍数，则可以根据状态机的输出使计数器可编程。 类似地，可以根据状态机的输出来动态调整相位检测器或环路滤波器的特性。 在本发明的另一方面，可编程逻辑电路的输出是或用于产生PLL中的相位检测器的输入之一。

公开(公告)号：US5247195A

公开(公告)日：1993-09-21

申请号：US736205

申请日：1991-07-26

申请人： John E. Turner ,  Om P. Agrawal

发明人： John E. Turner ,  Om P. Agrawal

IPC分类号： H03K19/177

CPC分类号： H03K19/17712

摘要： An industry standard programmable logic device capable of driving up to 64 milliamps in the output low state and up to 15 milliamps in the output high state. An output macrocell is described for use with such a driver, which includes a user-selectable D/T flip-flop, input hysteresis, and a programmable individually bypassable input latch with a common latch enable.

摘要翻译： 一种工业标准可编程逻辑器件，能够在输出低电平状态下驱动高达64毫安，输出高电平时可驱动高达15毫安。 描述了与这种驱动器一起使用的输出宏单元，其包括用户可选择的D / T触发器，输入滞后以及具有公共锁存器使能的可编程单独可旁路输入锁存器。

公开(公告)号：US5027315A

公开(公告)日：1991-06-25

申请号：US401528

申请日：1989-08-30

申请人： Om P. Agrawal ,  Joseph A. Brcich

发明人： Om P. Agrawal ,  Joseph A. Brcich

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1733 ,  H03K19/17716

摘要： The present invention provides an output logic macrocell for controlling configuration of an output for an integrated circuit wich provides a logic signal including a register responsive to a clock signal for latching the logic signal to provide a registered signal. An output selector receives both the logic signal and the registered signal and selects responsive to an output select signal, either the logic signal or the registered signal. A feedback path provides a feedback signal as data which is selected by a feedback selector responsive to a feedback select signal for selecting the logic signal or the registered signal as the feedback signal. Further, a clock signal enable circuit, responsive to a clock enable signal, enables or disables the clock signal to clock the register. Accordingly, the register, the output selector, the feedback path, and the clock enable circuit are all dynamically controllable by respective control signals.

摘要翻译： 本发明提供一种用于控制集成电路的输出配置的输出逻辑宏单元，其提供包括响应于时钟信号的寄存器的逻辑信号，用于锁存逻辑信号以提供注册信号。 输出选择器接收逻辑信号和注册信号，并且响应输出选择信号选择逻辑信号或登记信号。 反馈路径提供反馈信号作为响应于用于选择逻辑信号或注册信号作为反馈信号的反馈选择信号的反馈选择器选择的数据。 此外，响应于时钟使能信号的时钟信号使能电路启用或禁用时钟信号来对寄存器进行时钟。 因此，寄存器，输出选择器，反馈路径和时钟使能电路都可以通过相应的控制信号动态地控制。

公开(公告)号：US5015884A

公开(公告)日：1991-05-14

申请号：US490808

申请日：1990-03-07

申请人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

IPC分类号： H01L21/82 ,  H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： A high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. Further, the switch matrix provides centralized global routing with a fixed path independent delay. The programmable switch interconnection matrix decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O marcrocells decouple the logic macrocells from the package I/O pins. Thus, the architecture of this invention is easily scalable to higher density devices without compromising speed. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell.

摘要翻译： 高密度分段可编程阵列逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程逻辑宏单元，可编程输入/输出宏单元，逻辑分配器和可编程产品项阵列。 此外，交换矩阵提供具有固定路径独立延迟的集中式全局路由。 可编程开关互连矩阵将逻辑宏单元与产品项阵列分离。 逻辑分配器将产品项阵列与逻辑宏单元分离，I / O马尔克罗尔将逻辑宏单元与封装I / O引脚分离。 因此，本发明的架构可以容易地扩展到更高密度的设备而不会影响速度。 逻辑分配器将产品术语从产品术语数组转向选定的逻辑宏单元，使得不将产品术语永久分配给特定的逻辑宏单元。

公开(公告)号：US20160094961A1

公开(公告)日：2016-03-31

申请号：US14868299

申请日：2015-09-28

申请人： Om P. Agrawal ,  Anita Agrawal

发明人： Om P. Agrawal ,  Anita Agrawal

IPC分类号： H04W4/14 ,  H04L12/58

CPC分类号： H04W4/14 ,  H04L51/30 ,  H04L51/34 ,  H04L51/36 ,  H04L51/38

摘要： A method for efficiently transmitting bulk data over a mobile network using predetermined fillable templates may include correlating records in a database with an input field of a predetermined fillable template and a report field of a predetermined report. The template may be provided to a user by way of a downloadable and executable mobile application. The method may include receiving discrete SMS messages populated into the input fields of the template by a user of a mobile device upon which the mobile application has been installed. The method may include associating each received SMS message with a corresponding report field of the predetermined report according. The method may include populating the corresponding report field of the predetermined report with report information based on the received SMS message. The method may also include providing the predetermined report to a computing device associated with a second user.

摘要翻译： 可以使用预定的可填写模板通过移动网络高效地发送批量数据的方法可以包括将数据库中的记录与预定可填写模板的输入字段和预定报告的报告字段相关联。 可以通过可下载和可执行的移动应用程序将模板提供给用户。 该方法可以包括由安装移动应用的移动设备的用户接收填充到模板的输入字段中的离散SMS消息。 该方法可以包括将每个接收到的SMS消息与预定报告的相应报告字段相关联。 该方法可以包括基于接收到的SMS消息填充具有报告信息的预定报告的相应报告字段。 该方法还可以包括向与第二用户相关联的计算设备提供预定报告。

公开(公告)号：US07957208B1

公开(公告)日：2011-06-07

申请号：US12389149

申请日：2009-02-19

申请人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

发明人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

IPC分类号： G11C7/00

CPC分类号： H03K19/17772 ,  G11C29/028 ,  H03K19/1776

摘要： In one embodiment, a programmable logic device includes a plurality of logic blocks; a plurality of input/output blocks; volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks; embedded block RAM adapted to store user data; flash memory having at least a first partition and a second partition; and a data port adapted to provide external device access to the first partition of the non-volatile memory. The flash memory is adapted to store within the first partition user data from the data port and is further adapted to store within the second partition user data from the embedded block RAM.

摘要翻译： 在一个实施例中，可编程逻辑器件包括多个逻辑块; 多个输入/输出块; 易失性配置存储器，其适于存储用于配置逻辑块和输入/输出块的配置数据; 适用于存储用户数据的嵌入式块RAM; 闪存具有至少第一分区和第二分区; 以及适于提供对所述非易失性存储器的所述第一分区的外部设备访问的数据端口。 闪存适于在数据端口内的第一分区用户数据内存储，并且还适于在第二分区用户内存储来自嵌入式块RAM的数据。

公开(公告)号：US07427874B1

公开(公告)日：2008-09-23

申请号：US11949454

申请日：2007-12-03

申请人： Om P. Agrawal ,  Ravindar M. Lall ,  David L. Rutledge ,  Tom Gustafson

发明人： Om P. Agrawal ,  Ravindar M. Lall ,  David L. Rutledge ,  Tom Gustafson

IPC分类号： H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17796

摘要： A programmable logic device in accordance with an embodiment of the invention includes configurable logic blocks, embedded random access memory (RAM) blocks, and input/output blocks adapted to transfer information into or out of the programmable logic device. An interconnect architecture is adapted to route information among the configurable logic blocks, embedded RAM blocks, and input/output blocks within the programmable logic device. An interface block is provided that couples an embedded RAM block and an input/output block but not a logic block to the interconnect architecture.

摘要翻译： 根据本发明实施例的可编程逻辑器件包括可配置逻辑块，嵌入式随机存取存储器（RAM）块和适于将信息传入或传出可编程逻辑器件的输入/输出块。 互连架构适于在可编程逻辑器件内的可配置逻辑块，嵌入式RAM块和输入/输出块之间路由信息。 提供了将嵌入式RAM块和输入/输出块而不是逻辑块耦合到互连体系结构的接口块。

公开(公告)号：US07327160B1

公开(公告)日：2008-02-05

申请号：US11676196

申请日：2007-02-16

申请人： Om P. Agrawal ,  Jock Tomlinson ,  Kuang Chi ,  Ji Zhao ,  Ju Shen ,  Jinghui Zhu

发明人： Om P. Agrawal ,  Jock Tomlinson ,  Kuang Chi ,  Ji Zhao ,  Ju Shen ,  Jinghui Zhu

IPC分类号： H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17744

摘要： In one embodiment of the invention, a programmable integrated circuit includes a plurality of SERDES circuits; a plurality of input/output (I/O) circuits; and a routing structure configurable to provide one or more of the following connections over routing paths having deterministic routing delays: coupling a SERDES circuit to another SERDES circuit; coupling a SERDES circuit to an I/O circuit; coupling an I/O circuit to a SERDES circuit; and coupling an I/O circuit to another I/O circuit.

摘要翻译： 在本发明的一个实施例中，可编程集成电路包括多个SERDES电路; 多个输入/输出（I / O）电路; 以及可配置为通过具有确定性路由延迟的路由路径提供一个或多个以下连接的路由结构：将SERDES电路耦合到另一个SERDES电路; 将SERDES电路耦合到I / O电路; 将I / O电路耦合到SERDES电路; 并将I / O电路耦合到另一个I / O电路。

公开(公告)号：US06919736B1

公开(公告)日：2005-07-19

申请号：US10620286

申请日：2003-07-14

申请人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Bai Nguyen ,  Yu Huang ,  Jack Wong

发明人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Bai Nguyen ,  Yu Huang ,  Jack Wong

IPC分类号： G06F17/50 ,  H03K19/177

CPC分类号： H03K19/17796 ,  G06F17/5054

摘要： A field programmable gate array (FPGA) has plural columns of run-time memory provided in each of one or more partitions. Each column of run-time memory has a plurality of configurable memory blocks (CMB's). Each CMB is programmably configurable at least into a shallow-and-widest mode where data words have a maximum bit width and into a deep-and-narrowest mode where data words have a minimum bit width. Each CMB spans plural interconnect buses and the bits of its widest data words are distributed among the spanned interconnect buses. When a deep-and-narrow mode is invoked, CMB's of alternate columns operate in complementary fashion so that bits of narrowed words from one CMB move through a first subset of the interconnect buses while bits of narrowed words from a second CMB, in an alternate column, move through a second subset of the interconnect buses, where the second subset is mutually exclusive of the first subset of the interconnect buses. On the other hand, when the shallow-and-widest mode is invoked, the bits of the wide words of CMB's in alternate columns shared interconnect buses on an overlapping basis. In one embodiment, the shared interconnect buses are tri-statable. Programmable joiners are provided for joining or disjoining the tri-statable interconnect buses of adjacent partitions.

摘要翻译： 现场可编程门阵列（FPGA）具有在一个或多个分区中的每一个中提供的多列运行时存储器。 每列运行时存储器具有多个可配置存储器块（CMB）。 每个CMB可编程地至少配置为浅和最宽的模式，其中数据字具有最大位宽度，并且成为数据字具有最小位宽度的最深和最窄模式。 每个CMB跨越多个互连总线，其最宽的数据字的位分布在跨接互连总线之间。 当调用深而窄的模式时，CMB的备用列以互补方式运行，使得来自一个CMB的窄字的位移动通过互连总线的第一子集，同时来自第二CMB的窄字的位置 列移动穿过互连总线的第二子集，其中第二子集与互连总线的第一子集相互排斥。 另一方面，当调用浅和最宽模式时，CMB在备用列中的宽字的位以重叠的基础共享互连总线。 在一个实施例中，共享互连总线是三态的。 可编程连接器用于连接或分离相邻分区的三态互连总线。

公开(公告)号：US06885227B2

公开(公告)日：2005-04-26

申请号：US10629221

申请日：2003-07-29

申请人： Om P. Agrawal ,  Hans W. Klein ,  Geoffrey R. Rickard ,  Harald J. Weller

发明人： Om P. Agrawal ,  Hans W. Klein ,  Geoffrey R. Rickard ,  Harald J. Weller

IPC分类号： H03L7/089 ,  H03L7/099 ,  H03L7/18 ,  H03L7/06

CPC分类号： H03L7/0891 ,  H03L7/0995 ,  H03L7/0996 ,  H03L7/18

摘要： Systems and methods are disclosed to provide clock generation. In accordance with one embodiment, a clock generator chip is provided that is configurable and in-system programmable and includes a flexible skew control architecture. The clock generator chip may also provide programmable input circuits, programmable output circuits, and permit a JTAG boundary scan.