公开(公告)号：US09054675B2

公开(公告)日：2015-06-09

申请号：US13531341

申请日：2012-06-22

申请人： Kallol Mazumder ,  Jongtae Kwak ,  Tsugio Takahashi ,  Yasuo Satoh

发明人： Kallol Mazumder ,  Jongtae Kwak ,  Tsugio Takahashi ,  Yasuo Satoh

IPC分类号： H03H11/26

CPC分类号： H03H11/26

摘要： Apparatuses and methods related to adjusting a minimum forward path delay of a signal path are disclosed. One such signal path includes a signal path having a minimum forward path delay, wherein the signal path is configured to adjust the minimum forward path delay based at least in part on a selected latency and a propagation delay of the minimum forward path delay. An example method includes reducing a forward path delay of a command path by at least one clock cycle of a clock signal to provide a command according to a selected latency responsive to a count value representative of a minimum forward path delay of the command path being greater than a maximum count value for the selected latency.

摘要翻译： 公开了与调整信号路径的最小前向路径延迟相关的装置和方法。 一个这样的信号路径包括具有最小正向路径延迟的信号路径，其中信号路径被配置为至少部分地基于所选等待时间和最小前向路径延迟的传播延迟来调整最小前向路径延迟。 一个示例性方法包括：通过时钟信号的至少一个时钟周期来减少命令路径的前向路径延迟，以根据表示命令路径的最小前向路径延迟的计数值的选定延迟来提供命令更大 比所选延迟的最大计数值。

公开(公告)号：US08988966B2

公开(公告)日：2015-03-24

申请号：US13212015

申请日：2011-08-17

申请人： Jongtae Kwak

发明人： Jongtae Kwak

IPC分类号： G11C8/00 ,  G11C7/10 ,  G11C7/22 ,  H03L7/081

CPC分类号： G11C7/222 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  H03K3/012 ,  H03K3/0375 ,  H03L7/0814 ,  H03L7/181

摘要： A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.

摘要翻译： 描述了具有时钟同步电路和读等待时间控制电路的读等待时间控制电路。 时钟同步电路包括可调延迟线，以产生其相位与输入时钟信号的相位同步的输出时钟信号。 读等待时间控制电路相对于输入时钟信号的定时捕获读指令信号，并相对于输出时钟信号的定时输出读指令信号，使得输出指示读指令的读命令信号。

公开(公告)号：US08421515B2

公开(公告)日：2013-04-16

申请号：US13341418

申请日：2011-12-30

申请人： Jongtae Kwak ,  Kang Yong Kim

发明人： Jongtae Kwak ,  Kang Yong Kim

IPC分类号： H03K5/159 ,  H03L7/00 ,  H03L7/06

CPC分类号： H03L7/00 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814

摘要： A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

摘要翻译： 时钟同步系统和方法避免了高频时的输出时钟抖动，并且在粗略和精细延迟的边界处实现了平滑的相位转变。 系统可以使用配置成从输入参考时钟产生两个中间时钟并且在它们之间具有固定的相位差的延迟线。 相位混合器接收这两个中间时钟并产生具有在中间时钟的相位之间的相位的最终输出时钟。 在高时钟频率下在延迟线上的移位不影响馈入相位混频器的中间时钟之间的相位关系。 来自相位混频器的输出时钟与输入参考时钟同步，即使在高时钟频率输入时也不会出现任何抖动或噪音。

公开(公告)号：US20110254604A1

公开(公告)日：2011-10-20

申请号：US13171755

申请日：2011-06-29

申请人： Tyler Gomm ,  Kang Yong Kim ,  Jongtae Kwak

发明人： Tyler Gomm ,  Kang Yong Kim ,  Jongtae Kwak

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.

摘要翻译： 本文公开了一种VDL / DLL架构，其中至少将VDL，VccVDL的电源调节为输入信号（ClkIn）入口到VDL中的函数。 具体地说，当通过VDL的延迟相对较小（当入口点朝向VDL的右侧（或最小延迟）边缘）时，VccVDL被调节为较高，并且当延迟相对较高时（当入口点 朝向VDL的左侧（或最大延迟）边缘）。 这提供了在VDL的各个阶段的分级延迟，但是不需要分别设计每个阶段。 其他优点包括可在更宽的频率范围内操作的VDL / DLL设计，以及减少的级数，包括减少数量的缓冲级。 此外，当使用所公开的技术时，可以完全省去缓冲阶段。 另外，所公开的VDL架构可以用于可能有利的是通过作为VDL入口点的函数的可变延迟来延迟信号的任何情况。

公开(公告)号：US08026747B2

公开(公告)日：2011-09-27

申请号：US12633632

申请日：2009-12-08

申请人： Jongtae Kwak

发明人： Jongtae Kwak

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0805

摘要： An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay line delaying the first intermediate signal by a first delay amount; a second delay line delaying the first intermediate signal by a second delay amount; a third delay line delaying the second intermediate signal by a third delay amount; and a fourth delay line delaying the second intermediate signal by a fourth delay amount. The apparatus also includes a closed feedback loop for detecting and adjusting the second and fourth delay amount.

摘要翻译： 公开了一种用于多相时钟产生的装置和方法。 该装置的一个实施例包括产生从具有第一频率的时钟信号的第一边缘延迟的第一和第二中间信号的模块。 第一和第二中间信号中的每一个具有作为第一频率的一半的第二频率。 第一和第二中间信号的相位差彼此相差180°。 该装置还包括延迟第一中间信号第一延迟量的第一延迟线; 第二延迟线，延迟所述第一中间信号第二延迟量; 第三延迟线，延迟所述第二中间信号第三延迟量; 以及第四延迟线，延迟所述第二中间信号第四延迟量。 该装置还包括用于检测和调整第二和第四延迟量的闭合反馈回路。

公开(公告)号：US08018791B2

公开(公告)日：2011-09-13

申请号：US12683309

申请日：2010-01-06

申请人： Jongtae Kwak

发明人： Jongtae Kwak

IPC分类号： G11C8/00

CPC分类号： G11C7/222 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  H03K3/012 ,  H03K3/0375 ,  H03L7/0814 ,  H03L7/181

摘要： A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.

摘要翻译： 描述了具有时钟同步电路和读等待时间控制电路的读等待时间控制电路。 时钟同步电路包括可调延迟线，以产生其相位与输入时钟信号的相位同步的输出时钟信号。 读等待时间控制电路相对于输入时钟信号的定时捕获读指令信号，并相对于输出时钟信号的定时输出读指令信号，使得输出指示读指令的读命令信号。

公开(公告)号：US20100199117A1

公开(公告)日：2010-08-05

申请号：US12755664

申请日：2010-04-07

申请人： Jongtae Kwak

发明人： Jongtae Kwak

IPC分类号： G06F1/12

CPC分类号： G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F11/1679 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

摘要： An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback clock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit.

摘要翻译： 用于使输出时钟信号与输入时钟信号同步的装置包括第一定时同步电路，控制逻辑和计数器。 第一定时同步电路可操作以响应于选通信号产生代表输入时钟信号的参考时钟信号与代表输出时钟信号的反馈时钟信号的延迟。 控制逻辑可操作以基于参考时钟信号产生使能信号，并且基于反馈时钟信号产生选通信号。 该计数器可操作地计数在使能信号和选通信号之间出现的参考时钟信号的周期，以产生第一定时同步电路的循环计数。

公开(公告)号：US07728639B2

公开(公告)日：2010-06-01

申请号：US12247672

申请日：2008-10-08

申请人： Tyler Gomm ,  Eric Booth ,  Jongtae Kwak

发明人： Tyler Gomm ,  Eric Booth ,  Jongtae Kwak

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.

摘要翻译： 本文公开了改进的延迟锁定环（DLL）初始化电路，其改变用于通过使用三个时钟相位来初始化可变延迟线的延迟（例如，入口点或出口点）的测量：DLL参考时钟（输入到延迟线） ，由延迟Tref修整的参考时钟，以及由延迟Tfb修剪的反馈时钟。 通过在适当的时间使用这三个相，测量意识到正（Tref）和负（Tfb）修整的Tac修整。 具体地，测量“起始”和“停止”信号每个仅通过延迟Tref和Tfb中的一个，使得测量中的误差是Tref和Tfb两者的函数。 这提高了测量的精度，使得在初始化之后不需要额外的DLL的移位，并且即使对于高时钟频率也允许宽的修整范围。

公开(公告)号：US20100085095A1

公开(公告)日：2010-04-08

申请号：US12633632

申请日：2009-12-08

申请人： Jongtae Kwak

发明人： Jongtae Kwak

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0805

摘要： An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay line delaying the first intermediate signal by a first delay amount; a second delay line delaying the first intermediate signal by a second delay amount; a third delay line delaying the second intermediate signal by a third delay amount; and a fourth delay line delaying the second intermediate signal by a fourth delay amount. The apparatus also includes a closed feedback loop for detecting and adjusting the second and fourth delay amount.

摘要翻译： 公开了一种用于多相时钟产生的装置和方法。 该装置的一个实施例包括产生从具有第一频率的时钟信号的第一边缘延迟的第一和第二中间信号的模块。 第一和第二中间信号中的每一个具有作为第一频率的一半的第二频率。 第一和第二中间信号的相位差彼此相差180°。 该装置还包括延迟第一中间信号第一延迟量的第一延迟线; 第二延迟线，延迟所述第一中间信号第二延迟量; 第三延迟线，延迟所述第二中间信号第三延迟量; 以及第四延迟线，延迟所述第二中间信号第四延迟量。 该装置还包括用于检测和调整第二和第四延迟量的闭合反馈回路。

公开(公告)号：US20090243689A1

公开(公告)日：2009-10-01

申请号：US12483092

申请日：2009-06-11

申请人： Jongtae Kwak

发明人： Jongtae Kwak

IPC分类号： H03H11/26

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K19/01707 ,  H03K19/01721 ,  H03K2005/00052 ,  H03K2005/00065 ,  H03K2005/00215

摘要： Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay line to synchronize two clock signals.

摘要翻译： 描述包括时钟混合电路以提供可选择的传播时间的延迟电路。 来自混合电路的输出信号通过可变延迟线选择性耦合，以同步两个时钟信号。