公开(公告)号：US06732326B2

公开(公告)日：2004-05-04

申请号：US09846477

申请日：2001-04-30

申请人： Eun-A Choi ,  Jin-Ho Kim ,  Nae-Soo Kim ,  Deock-Gil Oh

发明人： Eun-A Choi ,  Jin-Ho Kim ,  Nae-Soo Kim ,  Deock-Gil Oh

IPC分类号： H03M1341

CPC分类号： H03M13/6362 ,  H03M13/395 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/4107

摘要： A structure and a method for depuncturing an input bit stream being input to a Viterbi decoder when the Viterbi decoder is designed by using a Radix-4 branch metric calculator in a method for designing the Viterbi decoder that decodes a punctured code at a high-speed, are disclosed. A depuncture structure for Radix-4 branch metric calculation in a high-speed Viterbi decoder includes four FIFOs, four multiplexers, and one Radix-4 branch metric calculator. Two input bit streams of I and Q are connected to two upper FIFOs and two lower FIFOs. An output terminal of FIFO is connected to upper and lower multiplexers of the next stage. One output terminal of each multiplexer is connected to Radix-4 branch metric calculator. As a result, Radix-4 branch metric calculation can be achieved by using the same clock as a clock speed of the input I and Q bit streams. This structure and this method can be applied to a depuncturing process for Radix-4 branch metric calculation of all punctured codes derived from ½ code.

摘要翻译： 在维特比解码器被设计成通过在设计维特比解码器的方法中设计的维特比解码器的结构和方法被输入到维特比解码器，该维特比解码器以高速解码穿孔码 ，被披露。 在高速维特比解码器中用于基数4分支度量计算的解穿孔结构包括四个FIFO，四个多路复用器和一个基数-4分支度量计算器。 I和Q的两个输入比特流连接到两个较高的FIFO和两个较低的FIFO。 FIFO的输出端子连接到下一级的上下复用器。 每个多路复用器的一个输出端连接到基数-4分支度量计算器。 因此，可以通过使用与输入I和Q位流的时钟速度相同的时钟来实现基数-4分支度量计算。 该结构和该方法可以应用于从½码导出的所有穿孔码的基数-4分支度量计算的解穿孔过程。

公开(公告)号：US07546509B2

公开(公告)日：2009-06-09

申请号：US10547236

申请日：2003-12-30

申请人： Soo Young Kim ,  Deock-Gil Oh ,  Jae-Moung Kim

发明人： Soo Young Kim ,  Deock-Gil Oh ,  Jae-Moung Kim

IPC分类号： H03M13/00

CPC分类号： H03M13/2963 ,  H03M13/033 ,  H03M13/152 ,  H03M13/29 ,  H03M13/2909 ,  H03M13/2918 ,  H03M13/47 ,  H03M13/635 ,  H03M13/6368 ,  H03M13/6381 ,  H04L1/0009 ,  H04L1/0057 ,  H04L1/0069 ,  H04L1/1819

摘要： The rate compatible code is formed by forming an m dimensional product code by using a systematic block code in a predetermined number of axes: The m dimensional product code is divided into an information block and 2m−1 parity blocks. Indices are allocated to the divided blocks of the information block and 2m−1 parity blocks. Combinations of the information block and corresponding parity blocks adjacent to the information block are obtained. A first weighting factor w1 for the combinations is estimated and saved. Another parity block adjacent to the saved combination is found and a new combination is formed. The first weighting factor w1 for the new combination is estimated. If there are combinations having the same first weighting factor w1, a second weighting factor w2 for the combinations is estimated and the combinations having a smaller value of w2 are neglected. Rate compatible having the combinations are formed.

摘要翻译： 速率兼容代码通过使用预定数量的轴中的系统块代码形成m维乘积代码形成：m维乘积代码被划分为信息块和2m-1个奇偶校验块。 指数被分配给信息块的分割块和2m-1个奇偶校验块。 获得与信息块相邻的信息块和对应的奇偶校验块的组合。 估计并保存组合的第一加权系数w1。 找到与保存的组合相邻的另一个奇偶校验块，并形成新的组合。 估计新组合的第一加权因子w1。 如果存在具有相同第一加权因子w1的组合，则估计用于组合的第二加权因子w2，并且忽略具有较小值w2的组合。 具有组合的速率兼容。

公开(公告)号：US07539920B2

公开(公告)日：2009-05-26

申请号：US11265451

申请日：2005-11-02

申请人： Eun-A Choi ,  Nae-Soo Kim ,  Deock-Gil Oh ,  Ji-Won Jung

发明人： Eun-A Choi ,  Nae-Soo Kim ,  Deock-Gil Oh ,  Ji-Won Jung

IPC分类号： H03M13/00

CPC分类号： H03M13/11

摘要： Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.

摘要翻译： 提供了一种使用具有部分组的顺序解码算法的LDPC解码装置和方法，其能够将迭代解码的数量减少一半以上，而不降低性能并增加计算量。 LDPC解码方法包括以下步骤：基于与接收到的噪声相关的星座中的符号信号与LDPC编码数据之间的距离相关的信道值的信息，以及初始化比特节点，接收先验概率信息（信道值） 在根据先验概率信息更新校验节点信息之前，将校验节点划分为部分组，并通过应用顺序解码算法执行解码; 确定是否满足奇偶校验方程; 并输出在满足奇偶校验方程时获得的解码消息，或者通过终止算法终止迭代处理器。

公开(公告)号：US20080285685A1

公开(公告)日：2008-11-20

申请号：US12096119

申请日：2006-12-07

申请人： Dae-Ig Chang ,  Deock-Gil Oh ,  Kwang-Min Hyun ,  Dong-Weon Yoon ,  Sang-Kyu Park

发明人： Dae-Ig Chang ,  Deock-Gil Oh ,  Kwang-Min Hyun ,  Dong-Weon Yoon ,  Sang-Kyu Park

IPC分类号： H04L27/38

CPC分类号： H04L25/067 ,  H04L1/005 ,  H04L27/38

摘要： Provided are an apparatus and method for generating a soft bit metric and a multi-level (M-ary) Quadrature Amplitude Modulation (QAM) receiving system using the same. The apparatus includes an analog to digital converter for converting an analog symbol signal of a demodulated I (Inphase) or Q (Quadrature) channel into a digital signal, a sealer for scaling the converted digital signal based on a reference value used for determining a space between symbols, a positive integer converter for calculating a positive integer of the scaled digital I or Q channel symbol signal, a sign determinator for determining a sign of the scaled digital I or Q channel symbol signal, and a bit information converter for converting the scaled digital I or Q channel symbol signal into soft bit metric information per bit on the basis of the calculated positive integer and the determined sign value.

摘要翻译： 提供了一种用于生成软比特度量的装置和方法以及使用其的多级（M元）正交幅度调制（QAM）正交调制（QAM）接收系统。 该装置包括用于将解调的I（同相）或Q（正交）信道的模拟符号信号转换为数字信号的模数转换器，用于基于用于确定空间的参考值缩放转换的数字信号的缩放器 在符号之间，用于计算缩放的数字I或Q信道符号信号的正整数的正整数转换器，用于确定缩放的数字I或Q信道符号信号的符号的符号确定器，以及用于将缩放的 基于计算的正整数和确定的符号值，将数字I或Q通道符号信号转换为每位的软比特度量信息。

公开(公告)号：US20070150789A1

公开(公告)日：2007-06-28

申请号：US11607592

申请日：2006-11-30

申请人： Eun-A Choi ,  Dae-Ig Chang ,  Deock-Gil Oh

发明人： Eun-A Choi ,  Dae-Ig Chang ,  Deock-Gil Oh

IPC分类号： H03M13/00

CPC分类号： H03M13/1165 ,  H03M13/1111

摘要： Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing a Read Only Memory (ROM) index, an address index and a permutation index for the stored data; a check node updating unit for bring the stored data in parallel based on the ROM index, the address index, and the permutation index and updating a check node; and a bit node updating unit for updating a bit node based on the data stored in the memory and check node information updated in the check node updating unit.

摘要翻译： 提供了一种使用类型分类索引的低密度奇偶校验（LDPC）解码装置和方法。 该装置包括：存储器分配单元，用于将接收数据乘以估计的信道值，并将乘法值存储在包括多个存储块的存储器中; 索引存储单元，用于存储所存储的数据的只读存储器（ROM）索引，地址索引和置换索引; 检查节点更新单元，用于基于所述ROM索引，所述地址索引和所述置换索引并行存储所述数据，并更新校验节点; 以及位节点更新单元，用于基于存储在存储器中的数据更新位节点，并且校验在校验节点更新单元中更新的节点信息。

公开(公告)号：US20070092041A1

公开(公告)日：2007-04-26

申请号：US11442078

申请日：2006-05-25

申请人： Il-Han Kim ,  Joon-Gyu Ryu ,  Ho-Kyom Kim ,  Deock-Gil Oh

发明人： Il-Han Kim ,  Joon-Gyu Ryu ,  Ho-Kyom Kim ,  Deock-Gil Oh

IPC分类号： H04L27/22

CPC分类号： H04L27/0012 ,  H04L27/22

摘要： Provided are an apparatus and method for robust Binary Phase Shift Keying/Quadrature Phase Shift Keying (BPSK/QPSK) blind modulation classification against errors in a satellite communication system. The apparatus includes first and second likelihood value calculators for calculating a likelihood value of a received baseband signal each for of BPSK and QPSK modulation modes, respectively, a maximum setting unit for deriving a maximum value of the likelihood values or ith likelihood ratios calculated by the first and second likelihood value calculators and setting a flag for the maximum value to “1” and a flag for the remaining value to “0”, first and second flag combining units for combining the flags for the modulation modes, respectively, a modulation mode flag setting unit for selecting a maximum value from the flags combined by the first and second flag combining units, and a modulation classification mode deciding unit.

摘要翻译： 本发明提供了一种针对卫星通信系统中的错误的鲁棒二进制相移键控/正交相移键控（BPSK / QPSK）盲调制分类的装置和方法。 该装置包括：第一和第二似然值计算器，用于分别计算用于BPSK和QPSK调制模式的接收基带信号的似然值;最大设置单元，用于导出似然值的最大值或i < / SUP>似然比，并将最大值的标志设置为“1”，将剩余值的标志设置为“0”，第一和第二标志组合单元，用于组合用于 调制模式标志设置单元，用于从由第一和第二标志组合单元组合的标志中选择最大值，以及调制分类模式决定单元。

公开(公告)号：US08122315B2

公开(公告)日：2012-02-21

申请号：US11607592

申请日：2006-11-30

申请人： Eun-A Choi ,  Dae-Ig Chang ,  Deock-Gil Oh

发明人： Eun-A Choi ,  Dae-Ig Chang ,  Deock-Gil Oh

IPC分类号： H03M13/00

CPC分类号： H03M13/1165 ,  H03M13/1111

摘要： Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing a Read Only Memory (ROM) index, an address index and a permutation index for the stored data; a check node updating unit for bring the stored data in parallel based on the ROM index, the address index, and the permutation index and updating a check node; and a bit node updating unit for updating a bit node based on the data stored in the memory and check node information updated in the check node updating unit.

摘要翻译： 提供了一种使用类型分类索引的低密度奇偶校验（LDPC）解码装置和方法。 该装置包括：存储器分配单元，用于将接收数据乘以估计的信道值，并将乘法值存储在包括多个存储块的存储器中; 索引存储单元，用于存储所存储的数据的只读存储器（ROM）索引，地址索引和置换索引; 检查节点更新单元，用于基于所述ROM索引，所述地址索引和所述置换索引并行存储所述数据，并更新校验节点; 以及位节点更新单元，用于基于存储在存储器中的数据更新位节点，并且校验在校验节点更新单元中更新的节点信息。

公开(公告)号：US08116406B2

公开(公告)日：2012-02-14

申请号：US12096119

申请日：2006-12-07

申请人： Dae-Ig Chang ,  Deock-Gil Oh ,  Kwang-Min Hyun ,  Dong-Weon Yoon ,  Sang-Kyu Park

发明人： Dae-Ig Chang ,  Deock-Gil Oh ,  Kwang-Min Hyun ,  Dong-Weon Yoon ,  Sang-Kyu Park

IPC分类号： H04L27/00

CPC分类号： H04L25/067 ,  H04L1/005 ,  H04L27/38

摘要： Provided are an apparatus and method for generating a soft bit metric and a multi-level (M-ary) Quadrature Amplitude Modulation (QAM) receiving system using the same. The apparatus includes an analog to digital converter for converting an analog symbol signal of a demodulated I (Inphase) or Q (Quadrature) channel into a digital signal, a scaler for scaling the converted digital signal based on a reference value used for determining a space between symbols, a positive integer converter for calculating a positive integer of the scaled digital I or Q channel symbol signal, a sign determinator for determining a sign of the scaled digital I or Q channel symbol signal, and a bit information converter for converting the scaled digital I or Q channel symbol signal into soft bit metric information per bit on the basis of the calculated positive integer and the determined sign value.

摘要翻译： 提供了一种用于生成软比特度量的装置和方法以及使用其的多级（M元）正交幅度调制（QAM）正交调制（QAM）接收系统。 该装置包括用于将解调的I（同相）或Q（正交）信道的模拟符号信号转换为数字信号的模数转换器，用于根据用于确定空间的参考值对转换的数字信号进行缩放的缩放器 在符号之间，用于计算缩放的数字I或Q信道符号信号的正整数的正整数转换器，用于确定缩放的数字I或Q信道符号信号的符号的符号确定器，以及用于将缩放的 基于计算的正整数和确定的符号值，将数字I或Q通道符号信号转换为每位的软比特度量信息。

公开(公告)号：US20070130598A1

公开(公告)日：2007-06-07

申请号：US11607637

申请日：2006-11-30

申请人： Eun-A Choi ,  Nae-Soo Kim ,  Dae-Ig Chang ,  Deock-Gil Oh

发明人： Eun-A Choi ,  Nae-Soo Kim ,  Dae-Ig Chang ,  Deock-Gil Oh

IPC分类号： H04N7/173 ,  H04N7/18 ,  H04N7/16 ,  H04N7/20

CPC分类号： H04L12/2803 ,  H04B3/54 ,  H04B2203/5441 ,  H04B2203/5445 ,  H04L12/2801 ,  H04L12/2818 ,  H04L2012/2841 ,  H04L2012/2843 ,  H04N21/4131 ,  H04N21/4227 ,  H04N21/4355 ,  H04N21/43615 ,  H04N21/478 ,  H04N21/6143 ,  H04N21/6193 ,  H04N21/6547

摘要： Provided is a digital satellite broadcasting set-top box and a home network control system employing the same. The set-top box includes: a satellite signal receiving unit for receiving a satellite signal including a home network control signal for controlling the household appliances through a satellite broadcasting network from a remote terminal; and a control unit for extracting a household appliances control signal included in the satellite signal transmitted from the satellite signal receiving unit and commanding a power line converter to transmit the household appliances control signal to a corresponding household appliance, wherein the power line converter converts the household appliances control signal transmitted from the digital satellite broadcasting set-top box into a power line communication signal and transmits the power line communication signal on the home network through a power line.

摘要翻译： 提供了一种数字卫星广播机顶盒和采用其的家庭网络控制系统。 机顶盒包括：卫星信号接收单元，用于通过卫星广播网络从远程终端接收包括用于控制家用电器的家庭网络控制信号的卫星信号; 以及控制单元，用于提取从卫星信号接收单元发送的卫星信号中包含的家用电器控制信号，并指示电力线转换器将家用电器控制信号发送到相应的家用电器，其中电力线转换器将家庭 家用电器控制信号从数字卫星广播机顶盒发送到电力线通信信号，并通过电力线在家庭网络上发送电力线通信信号。

公开(公告)号：US07206333B2

公开(公告)日：2007-04-17

申请号：US10410832

申请日：2003-04-09

申请人： Kwon-Hue Choi ,  Soo-Young Kim ,  Kwang-Jae Lim ,  Deock-Gil Oh

发明人： Kwon-Hue Choi ,  Soo-Young Kim ,  Kwang-Jae Lim ,  Deock-Gil Oh

IPC分类号： H04B1/00

CPC分类号： H04L5/026

摘要： Disclosed is a method for using a different symbol timing for users so as to reduce a multiple access interference component in a multi-carrier code division multiple access (MC-CDMA) system. For this purpose, the presented invention involves dividing the users of the MC-CDMA system into two groups and applying an offset to the symbol timing between the user groups to cause a symbol transition of the opposite user group in the middle of the symbol interval, thereby reducing the multiple access interference component included in a symbol decision variable after a chip combination.

摘要翻译： 公开了一种对于用户使用不同的符号定时以减少多载波码分多址（MC-CDMA）系统中的多址干扰分量的方法。 为此，本发明涉及将MC-CDMA系统的用户划分成两组，并将偏移应用于用户组之间的符号定时，以在符号间隔的中间引起相对用户组的符号转换， 从而在芯片组合之后减少包括在符号判定变量中的多址干扰分量。