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    AC noise suppression from a bias signal in high voltage supply/low voltage device
    42.
    发明授权
    AC noise suppression from a bias signal in high voltage supply/low voltage device 有权
    高压电源/低压器件偏置信号的交流噪声抑制

    公开(公告)号：US08487691B1

    公开(公告)日：2013-07-16

    申请号：US13494282

    申请日：2012-06-12

    Applicant: Pankaj Kumar ,  Pramod Parameswaran ,  Vani Deshpande ,  Makeshwar Kothandaraman

    Inventor： Pankaj Kumar ,  Pramod Parameswaran ,  Vani Deshpande ,  Makeshwar Kothandaraman

    IPC: G05F1/10

    CPC classification number: H03F1/26 ,  H03F3/2171 ,  H03K19/00346

    Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first control voltage and a second control voltage. The second circuit may be configured to generate a bias signal in response to the first control voltage and the second control voltage. The third circuit may be configured to generate a filtered signal in response to the bias signal. The filtered signal may be added to the first control voltage and the second control voltage to provide AC noise suppression when generating the bias signal.

    Abstract translation: 一种包括第一电路，第二电路和第三电路的装置。 第一电路可以被配置为产生第一控制电压和第二控制电压。 第二电路可以被配置为响应于第一控制电压和第二控制电压而产生偏置信号。 第三电路可以被配置为响应于偏置信号产生滤波信号。 滤波后的信号可以被添加到第一控制电压和第二控制电压，以在产生偏置信号时提供AC噪声抑制。

    Multicasting Write Requests To Multiple Storage Controllers
    43.
    发明申请
    Multicasting Write Requests To Multiple Storage Controllers 审中-公开
    向多个存储控制器组播写请求

    公开(公告)号：US20110238909A1

    公开(公告)日：2011-09-29

    申请号：US12748764

    申请日：2010-03-29

    Applicant: Pankaj Kumar ,  James A. Mitchell

    Inventor： Pankaj Kumar ,  James A. Mitchell

    IPC: G06F12/16 ,  G06F17/30

    CPC classification number: G06F12/0866 ,  G06F11/1076 ,  G06F2212/262 ,  G06F2212/286

    Abstract: In one embodiment, the present invention includes a method for performing multicasting, including receiving a write request including write data and an address from a first server in a first canister, determining if the address is within a multicast region of a first system memory, and if so, sending the write request directly to the multicast region to store the write data and also to a mirror port of a second canister coupled to the first canister to mirror the write data to a second system memory of the second canister. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于执行多播的方法，包括从第一罐中的第一服务器接收包括写数据和地址的写请求，确定地址是否在第一系统存储器的多播区域内，以及 如果是，则将写入请求直接发送到多播区域以存储写入数据，并将该写请求发送到耦合到第一罐的第二罐的镜像端口，以将写入数据镜像到第二盒的第二系统存储器。 描述和要求保护其他实施例。

    I/O Buffer with Low Voltage Semiconductor Devices
    44.
    发明申请
    I/O Buffer with Low Voltage Semiconductor Devices 失效
    带低压半导体器件的I / O缓冲器

    公开(公告)号：US20100271118A1

    公开(公告)日：2010-10-28

    申请号：US12428556

    申请日：2009-04-23

    Applicant: Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

    Inventor： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

    IPC: G05F1/10

    CPC classification number: H03K17/0822 ,  H03K19/018528

    Abstract: Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

    Abstract translation: 所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。 第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。 第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。 从缓冲器的工作电压产生第一和第二偏置电压。 从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压 缓冲。 第三和第四偏置电压分别提供给第一和第二过压保护电路。

    Power detection system and circuit for high voltage supply and low voltage devices
    45.
    发明授权
    Power detection system and circuit for high voltage supply and low voltage devices 有权
    用于高压电源和低压器件的电源检测系统和电路

    公开(公告)号：US07800420B2

    公开(公告)日：2010-09-21

    申请号：US12346900

    申请日：2008-12-31

    Applicant: Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Anuroop Iyengar ,  Vani Deshpande

    Inventor： Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Anuroop Iyengar ,  Vani Deshpande

    IPC: H03L7/00

    CPC classification number: H03K17/223

    Abstract: A power detect system and circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices is disclosed. In one embodiment, the power detect system and circuit includes a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, and a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage. The power detect system further includes a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage.

    Abstract translation: 公开了一种用于检测低压器件的电路中的输入/输出电源电压（VDDIO）的电压电平的功率检测系统和电路。 在一个实施例中，功率检测系统和电路包括耦合在VDDIO和用于产生偏置电压的负电源电压（VSS）之间的分压器，耦合在核心电压（VDD）和VSS之间的第一反相器，用于产生第一 基于所述偏置电压的节点电压，耦合在所述VDDIO和所述VSS之间以产生基于所述偏置电压的第二节点电压的本机装置，以及耦合在所述第一反相器和所述本机装置之间的开关，用于基于 第一节点电压。 功率检测系统还包括耦合在VDD和VSS之间的第二反相器，用于基于第二节点电压产生输出电压。

    HIGH VOLTAGE INPUT RECEIVER USING LOW VOLTAGE TRANSISTORS
    46.
    发明申请
    HIGH VOLTAGE INPUT RECEIVER USING LOW VOLTAGE TRANSISTORS 有权
    使用低电压晶体管的高压输入接收器

    公开(公告)号：US20100026342A1

    公开(公告)日：2010-02-04

    申请号：US12185073

    申请日：2008-08-02

    Applicant: PRAMOD ELAMANNU PARAMESWARAN ,  Pankaj Kumar

    Inventor： PRAMOD ELAMANNU PARAMESWARAN ,  Pankaj Kumar

    IPC: H03K19/0175

    CPC classification number: H03K19/018528

    Abstract: A high voltage input receiver using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a comparator circuit and an inverter circuit. The comparator circuit includes a differential input module for generating a control signal by comparing an external voltage and a reference voltage, and a decision module for generating an inverter input signal based on the control signal. In addition, the reference voltage is used to set dc trip point of the input receiver. Moreover, the input receiver includes one or more stress protection modules to protect key components of the input receiver from exceeding their reliability limits.

    Abstract translation: 公开了一种使用低压晶体管的高压输入接收器。 在一个实施例中，输入接收器电路包括比较器电路和反相器电路。 比较器电路包括用于通过比较外部电压和参考电压来产生控制信号的差分输入模块和用于基于控制信号产生反相器输入信号的判定模块。 此外，参考电压用于设置输入接收器的直流跳变点。 此外，输入接收器包括一个或多个应力保护模块，用于保护输入接收器的关键部件不超出其可靠性限制。

    System and method for creating and maintaining data records to improve accuracy thereof
    47.
    发明申请
    System and method for creating and maintaining data records to improve accuracy thereof 审中-公开
    用于创建和维护数据记录以提高其精度的系统和方法

    公开(公告)号：US20060112133A1

    公开(公告)日：2006-05-25

    申请号：US11259986

    申请日：2005-10-26

    Applicant: Philip Ljubicich ,  David Camarillo ,  Pankaj Kumar

    Inventor： Philip Ljubicich ,  David Camarillo ,  Pankaj Kumar

    IPC: G06F17/00 ,  G06F7/00

    CPC classification number: G06F16/9024

    Abstract: In one example, a system receives, from different sources, data having various formats, the received data is selected and combined in accordance with the invention to create accurate records. Specifically, the inventive system organizes the received data into uniform data records having a predetermined format. The data in the uniform data records is converted, if necessary, to conform to a predetermined nomenclature, resulting in normalized data records. The normalized data records are then processed to extract and/or deduce information desired by users.

    Abstract translation: 在一个示例中，系统从不同的源接收具有各种格式的数据，根据本发明选择和组合接收的数据以创建准确的记录。 具体地，本发明的系统将接收到的数据组织成具有预定格式的统一数据记录。 如果需要，统一数据记录中的数据被转换成符合预定的命名，导致归一化的数据记录。 然后处理归一化的数据记录以提取和/或推导出用户期望的信息。

    Method of and system for computer system denial-of-service protection
    49.
    发明授权
    Method of and system for computer system denial-of-service protection 有权
    计算机系统拒绝服务保护的方法和系统

    公开(公告)号：US08701189B2

    公开(公告)日：2014-04-15

    申请号：US12322321

    申请日：2009-01-29

    Applicant: Suman Saraf ,  Sharad Agrawal ,  Pankaj Kumar

    Inventor： Suman Saraf ,  Sharad Agrawal ,  Pankaj Kumar

    IPC: G06F21/00

    CPC classification number: G06F21/566

    Abstract: A method of and system for protecting a computer system against denial-of-service attacks or other exploitation. The method comprises collecting network data and analyzing the network data using statistical and heuristic techniques to identify the source of the exploitation upon receiving an indication of exploitation. Upon identifying the network source, the network data associated with the network is blocked, redirected, or flow controlled. Preferably, the method also includes identifying when the system is being exploited.

    Abstract translation: 一种用于保护计算机系统免遭拒绝服务攻击或其他开发的方法和系统。 该方法包括收集网络数据并使用统计和启发式技术分析网络数据，以便在接收到开发指示时识别开发的来源。 在识别网络源时，与网络相关联的网络数据被阻塞，重定向或流量控制。 优选地，该方法还包括识别系统什么时候被利用。

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