公开(公告)号：US20050024933A1

公开(公告)日：2005-02-03

申请号：US10836651

申请日：2004-04-30

申请人： Fabio Pellizzer ,  Roberto Bez

发明人： Fabio Pellizzer ,  Roberto Bez

IPC分类号： H01L27/24 ,  H01L45/00 ,  G11C11/00

CPC分类号： H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126

摘要： A process for manufacturing a memory device having selector bipolar transistors for storage elements, includes the steps of: in a semiconductor body, forming at least a selector transistor, having at least an embedded conductive region, and forming at least a storage element, stacked on and electrically connected to the selector transistor; moreover, the step of forming at least a selector transistor includes forming at least a raised conductive region located on and electrically connected to the embedded conductive region.

摘要翻译： 一种用于制造具有用于存储元件的选择器双极晶体管的存储器件的方法，包括以下步骤：在半导体本体中，至少形成至少具有嵌入的导电区域的选择晶体管，并形成至少一个存储元件，堆叠在 并电连接到选择晶体管; 此外，形成至少选择晶体管的步骤包括至少形成位于并电连接到嵌入的导电区域的凸起的导电区域。

公开(公告)号：US06537879B2

公开(公告)日：2003-03-25

申请号：US09900501

申请日：2001-07-06

申请人： Roberto Bez ,  Emilio Camerlenghi ,  Stefano Ratti

发明人： Roberto Bez ,  Emilio Camerlenghi ,  Stefano Ratti

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

公开(公告)号：US20090014709A1

公开(公告)日：2009-01-15

申请号：US12169452

申请日：2008-07-08

申请人： Fabio Pellizzer ,  Augusto Benvenuti ,  Paolo Cappelletti ,  Roberto Bez ,  Agostino Pirovano

发明人： Fabio Pellizzer ,  Augusto Benvenuti ,  Paolo Cappelletti ,  Roberto Bez ,  Agostino Pirovano

IPC分类号： H01L29/06 ,  H01L21/82

CPC分类号： H01L27/1022 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

摘要： A process manufactures an array of cells in a body of semiconductor material wherein a common conduction region of a first conductivity type and a plurality of shared control regions, of a second conductivity type, are formed in the body. The shared control regions extend on the common conduction region and are laterally delimited by insulating regions. Then, a grid-like layer is formed on the body to delimit a first plurality of empty regions directly overlying the body and conductive regions of semiconductor material and the first conductivity type are formed by filling the first plurality of empty regions, each conductive region forming, together with the common conduction region and an own shared control region, a bipolar junction transistor.

摘要翻译： 一种方法制造半导体材料体中的单元阵列，其中在体内形成有第二导电类型的共同导电区域和多个第二导电类型的共用控制区域。 共享控制区域在公共导电区域上延伸并由绝缘区域侧向限定。 然后，在主体上形成网状层，以界定直接覆盖在主体和半导体材料的导电区域上的第一多个空区域，并且通过填充第一多个空区域形成第一导电类型，每个导电区域形成 与公共导电区域和自己的共用控制区域一起，双极结型晶体管。

公开(公告)号：US07468535B2

公开(公告)日：2008-12-23

申请号：US10713538

申请日：2003-11-14

申请人： Roberto Bez ,  Alessandro Grossi

发明人： Roberto Bez ,  Alessandro Grossi

IPC分类号： H01L29/76

CPC分类号： H01L21/76232 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11531

摘要： A process for self-aligned manufacturing of integrated electronic devices includes: forming, in a semiconductor wafer having a substrate, insulation structures that delimit active areas and project from the substrate; forming a first conductive layer, which coats the insulation structures and the active areas; and partially removing the first conductive layer. In addition, recesses are formed in the insulation structures before forming said first conductive layer.

摘要翻译： 一种用于集成电子器件的自对准制造的方法包括：在具有衬底的半导体晶片中形成限定有源区并从衬底突出的绝缘结构; 形成第一导电层，其涂覆绝缘结构和有源区; 并部分地去除第一导电层。 此外，在形成所述第一导电层之前，在绝缘结构中形成凹部。

公开(公告)号：US07372166B2

公开(公告)日：2008-05-13

申请号：US11258340

申请日：2005-10-24

申请人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

发明人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

IPC分类号： H01L23/48

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

摘要翻译： 电子半导体器件具有在第一导电区域和第二导电区域之间的亚光刻接触面积。 第一导电区域是杯状的并且具有垂直壁，其在顶部平面图中沿着细长形状的封闭线延伸。 第一导电区域的一个壁形成第一薄部分并且具有在第一方向上的第一尺寸。 第二导电区域具有第二薄部分，该第二薄部分具有横向于第一尺寸的第二方向的第二亚光刻尺寸。 第一和第二导电区域在其薄部分处直接电接触并形成亚光刻接触区域。 细长形状选择在第一方向上伸长的矩形和椭圆形之间。 因此，即使在限定导电区域的掩模之间存在小的不对准的情况下，接触区域的尺寸也保持近似恒定。

公开(公告)号：US07227171B2

公开(公告)日：2007-06-05

申请号：US10313991

申请日：2002-12-05

申请人： Roberto Bez ,  Fabio Pellizzer ,  Caterina Riva ,  Romina Zonca

发明人： Roberto Bez ,  Fabio Pellizzer ,  Caterina Riva ,  Romina Zonca

IPC分类号： H01L29/04

CPC分类号： G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691 ,  Y10S438/947

摘要： A contact structure, including a first conducting region having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region having a second thin portion with a second sublithographic dimension in a second direction transverse to said first direction; the first and second thin portions being in direct electrical contact and defining a contact area having a sublithographic extension. The thin portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer; the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic opening that is used to etch a mold opening in a mold layer and filling the mold opening.

摘要翻译： 一种接触结构，包括：第一导电区域，具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 第二导电区域，具有第二薄部分，具有横向于所述第一方向的第二方向的第二亚光刻尺寸; 第一和第二薄部分直接电接触并且限定具有亚光刻延伸部的接触区域。 使用沉积代替光刻获得薄部分：第一薄部分被放置在第一介电层中的开口的壁上; 通过在第一限定层的垂直壁上去除牺牲区域，在牺牲区域的自由侧上取代第二限定层，去除牺牲区域以形成用于蚀刻模具的亚光刻开口来获得第二薄部分 在模具层中开口并填充模具开口。

公开(公告)号：US07176553B2

公开(公告)日：2007-02-13

申请号：US10672293

申请日：2003-09-26

申请人： Alessandro Grossi ,  Roberto Bez ,  Giorgio Servalli

发明人： Alessandro Grossi ,  Roberto Bez ,  Giorgio Servalli

IPC分类号： H01L29/00

CPC分类号： H01L28/20 ,  H01L27/0802

摘要： In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a pre-determined resistivity is then formed in the active area (15). Prior to forming the resistive region (21), however, a delimitation structure (20) for delimiting the resistive region (21) is obtained on top of the active area (15). Subsequently, protective elements (25) are obtained which extend within the delimitation structure (20) and coat the resistive region (21).

摘要翻译： 在制造具有防止硅化物的集成电阻元件的工艺中，至少一个有源区域（15）在半导体晶片（10）中界定。 然后在有源区域（15）中形成具有预定电阻率的至少一个电阻区域（21）。 然而，在形成电阻区域（21）之前，在有源区域（15）的顶部获得用于限定电阻区域（21）的限定结构（20）。 随后，获得在限定结构（20）内延伸并涂覆电阻区（21）的保护元件（25）。

公开(公告)号：US07135756B2

公开(公告)日：2006-11-14

申请号：US10680727

申请日：2003-10-07

申请人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

发明人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

IPC分类号： H01L27/102

CPC分类号： H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

摘要： A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

摘要翻译： 单元阵列由多个单元形成，每个单元包括选择双极晶体管和存储组件。 电池阵列形成在包括P型共用集电极区域的主体中; 多个N型基极区，覆盖在公共集电极区域上; 在基区中形成多个P型发射极区; 以及形成在所述基极区域中的多个N型基极接触区域和比所述基极区域更高的掺杂水平的基极接触区域，其中每个基极区域由至少两个相邻的双极晶体管共享。

公开(公告)号：US20060202245A1

公开(公告)日：2006-09-14

申请号：US11337787

申请日：2006-01-23

申请人： Paola Zuliani ,  Fabio Pellizzer ,  Roberto Bez

发明人： Paola Zuliani ,  Fabio Pellizzer ,  Roberto Bez

IPC分类号： H01L29/94

CPC分类号： H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： A phase-change memory device, wherein memory cells form a memory array arranged in rows and columns. The memory cells are formed by a MOS selection device and a phase-change region connected to the selection device. The selection device is formed by first and second conductive regions which extend in a semiconductor substrate and are spaced from one another via a channel region, and by an isolated control region connected to a respective row and overlying the channel region. The first conductive region is connected to a connection line extending parallel to the rows, the second conductive region is connected to the phase-change region, and the phase-change region is connected to a respective column. The first connection line is a metal interconnection line and is connected to the first conductive region via a source-contact region made as point contact and distinct from the first connection line.

摘要翻译： 一种相变存储器件，其中存储器单元形成以行和列布置的存储器阵列。 存储单元由连接到选择装置的MOS选择装置和相变区域形成。 选择装置由在半导体衬底中延伸并且经由沟道区彼此间隔开的第一和第二导电区域以及连接到相应行并且覆盖沟道区域的隔离控制区域形成。 第一导电区域连接到与行平行延伸的连接线，第二导电区域连接到相变区域，并且相变区域连接到相应的列。 第一连接线是金属互连线，并且通过作为点接触而不同于第一连接线的源极接触区域连接到第一导电区域。

公开(公告)号：US06972430B2

公开(公告)日：2005-12-06

申请号：US10371154

申请日：2003-02-20

申请人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

发明人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

IPC分类号： G11C11/56 ,  H01L27/24 ,  H01L45/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

摘要翻译： 电子半导体器件具有在第一导电区域和第二导电区域之间的亚光刻接触面积。 第一导电区域是杯状的并且具有垂直壁，其在顶部平面图中沿着细长形状的封闭线延伸。 第一导电区域的一个壁形成第一薄部分并且具有在第一方向上的第一尺寸。 第二导电区域具有第二薄部分，该第二薄部分具有横向于第一尺寸的第二方向的第二亚光刻尺寸。 第一和第二导电区域在其薄部分处直接电接触并形成亚光刻接触区域。 细长形状选择在第一方向上伸长的矩形和椭圆形之间。 因此，即使在限定导电区域的掩模之间存在小的不对准的情况下，接触区域的尺寸也保持近似恒定。