公开(公告)号：US11876085B2

公开(公告)日：2024-01-16

申请号：US17358838

申请日：2021-06-25

Applicant: QUALCOMM Incorporated

Inventor： Abinash Roy ,  Lohith Kumar Vemula ,  Bharani Chava ,  Jonghae Kim

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/64 ,  H01G4/232

CPC classification number: H01L25/16 ,  H01L21/4803 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/642 ,  H01G4/232

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first interconnect and a second interconnect, a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal, a first solder interconnect coupled to a first side surface of the first terminal and the first interconnect, and a second solder interconnect coupled to a second side surface of the second terminal and the second interconnect.

公开(公告)号：US11817379B2

公开(公告)日：2023-11-14

申请号：US16927823

申请日：2020-07-13

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Milind Shah ,  Periannan Chidambaram

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/18 ,  H01L23/498 ,  H03F3/213 ,  H05K1/16

CPC classification number: H01L23/49822 ,  H03F3/213 ,  H05K1/111 ,  H05K1/16 ,  H05K1/181 ,  H05K1/185 ,  H05K1/0231 ,  H05K1/0233

Abstract: A package that includes a power amplifier and a substrate coupled to the power amplifier. The substrate includes an encapsulation layer, a capacitor device located in the encapsulation layer, an inductor located in the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer. The plurality of first interconnects is coupled to the capacitor device and the inductor. The inductor and the capacitor device are configured to be electrically coupled together to operate as elements of a matching network for the power amplifier. The capacitor device is configured to be coupled to ground.

公开(公告)号：US11817365B2

公开(公告)日：2023-11-14

申请号：US16883812

申请日：2020-05-26

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Jonghae Kim

IPC: H01L23/367 ,  H01L23/373 ,  H01L21/3065 ,  H01L21/48 ,  H01L21/306 ,  H01L21/322

CPC classification number: H01L23/367 ,  H01L21/3065 ,  H01L21/4882 ,  H01L23/3736 ,  H01L21/30604 ,  H01L21/3221

Abstract: A semiconductor device includes a die having one or more trenches on a back side of the die. The semiconductor device also includes a layer of thermally conductive material deposited on the back side of the die to fill the one or more trenches to form one or more plated trenches. The size (e.g., surface area or thickness (Z-height)) or location of the plated trenches may be determined based on one or more heat generating elements such as logic devices (CPU or GPU, for example) on an active side of the die. The thermally conductive material, which may be a metal such as copper (Cu) or silver (Ag), has a heat dissipation coefficient that is greater than a heat dissipation coefficient of a substrate of the die.

公开(公告)号：US11594804B2

公开(公告)日：2023-02-28

申请号：US16910025

申请日：2020-06-23

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Sang-June Park ,  Jonghae Kim

IPC: H01Q13/18 ,  H01Q1/12 ,  H01Q23/00

Abstract: Disclosed is an antenna on glass (AOG) device having an air cavity at least partially formed in a photosensitive glass substrate. An air cavity structure is at least partially encloses the air cavity and wherein the air cavity structure at least partially formed from the photosensitive glass substrate. An antenna is formed from portion of a top conductive layer disposed on a top surface of the air cavity structure and at least partially overlapping the air cavity. A metallization structure is provided having a bottom conductive layer disposed on a bottom surface of the air cavity structure, wherein the bottom conductive layer is electrically coupled to the top metal layer by a conductive pillar disposed through the photosensitive glass substrate. In addition, the AOG device may integrate one or more MIM capacitors and/or inductors that allow for RF filtering and impedance matching.

公开(公告)号：US11515289B2

公开(公告)日：2022-11-29

申请号：US17015308

申请日：2020-09-09

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Stanley Seungchul Song ,  Abinash Roy ,  Jonghae Kim

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

Abstract: An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.

公开(公告)号：US11444068B2

公开(公告)日：2022-09-13

申请号：US16928939

申请日：2020-07-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jonghae Kim ,  Periannan Chidambaram ,  Pratyush Kamal

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L21/762 ,  H01L21/48

Abstract: An integrated circuit (IC) package is described. The IC package includes a power delivery network. The IC package also includes a first die having a first surface and a second surface, opposite the first surface. The second surface is on a first surface of the power delivery network. The IC package further includes a second die having a first surface on the first surface of the first die. The IC package also includes package bumps on a second surface of the power delivery network, opposite the first surface of the power delivery network. The package bumps are coupled to contact pads of the power delivery network.

公开(公告)号：US11380678B2

公开(公告)日：2022-07-05

申请号：US16899811

申请日：2020-06-12

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Je-Hsiung Lan ,  Jonghae Kim

IPC: H01L27/06 ,  H01L21/8252 ,  H01L29/66

Abstract: A semiconductor device having metamorphic high electron mobility transistor (HEMT)-heterojunction bipolar transistor (HBT) integration on a semiconductor substrate. An example semiconductor device generally includes a semiconductor substrate, a bipolar junction transistor (BJT) disposed above the semiconductor substrate and comprising indium, and a HEMT disposed above the semiconductor substrate and comprising indium.

公开(公告)号：US11320847B2

公开(公告)日：2022-05-03

申请号：US16804474

申请日：2020-02-28

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Ravindra Vaman Shenoy ,  Milind Shah ,  Evgeni Gousev ,  Periannan Chidambaram

IPC: G05F1/56 ,  H01F27/28 ,  H01F41/04 ,  H02M7/155

Abstract: Reducing the space occupied by a voltage regulation integrated circuit (IC) that includes an inductor is achieved by implementing the inductor as a 3D inductor having windings formed of conductive elements integrated into a lower substrate, a circuit layer, and an upper substrate, and positioning other components within a core space of the 3D inductor in the circuit layer. The space occupied by the inductor is shared with the other circuit components and with the structural layers of the voltage regulation IC. A voltage regulation IC may be a switched-mode power supply (SMPS) that includes an inductor with a capacitor and/or a switching circuit. The inductor is implemented as upper horizontal traces in an upper substrate, lower horizontal traces in a lower substrate, and vertical interconnects in a circuit layer between the upper substrate and the lower substrate, and the conductive elements form the 3D inductor as a rectangular coil.

公开(公告)号：US11296024B2

公开(公告)日：2022-04-05

申请号：US16875579

申请日：2020-05-15

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Jonghae Kim

IPC: H01L23/528 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31

Abstract: An integrated circuit (IC) package is described. The IC package includes back-end-of-line layers on a substrate. The IC package also includes a nested interconnect structure on the back-end-of-line layers on the substrate. The nested interconnect structure is composed of an inner core pad and an outer ring pad in a concentric arrangement. The IC package further includes a redistribution layer on the nested interconnect structure. The IC package also includes an under bump metallization layer on the redistribution layer to support package balls.

公开(公告)号：US11189686B2

公开(公告)日：2021-11-30

申请号：US16798161

申请日：2020-02-21

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Milind Shah ,  Periannan Chidambaram

IPC: H01L49/02 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48

Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and a capacitor structure located between the substrate and the integrated device. The capacitor structure includes a capacitor substrate comprising a first trench, a first electrically conductive layer located in the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer. The first electrically conductive layer over the first trench, the dielectric layer and the second electrically conductive layer are configured as a first capacitor.