公开(公告)号：US09385305B2

公开(公告)日：2016-07-05

申请号：US13770306

申请日：2013-02-19

Applicant: QUALCOMM Incorporated

Inventor： William H. Xia ,  Wenqing Wu ,  Kendrick H. Yuen ,  Abhishek Banerjee ,  Xia Li ,  Seung H. Kang ,  Jung Pill Kim

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  H01L43/08 ,  H01L43/12

Abstract: A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current.

Abstract translation: 存储单元包括耦合到磁隧道结（MTJ）结构的细长第一电极和与耦合到MTJ结构的细长第一电极对准的细长第二电极。 细长电极被配置为引导开关电流感应磁场的相互添加部分通过MTJ。 响应于开关电流的应用，相互添加的部分增强MTJ的切换。

公开(公告)号：US09230630B2

公开(公告)日：2016-01-05

申请号：US14072599

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G11C11/16 ,  H04L9/30 ,  H04L9/08 ,  H04L9/32

CPC classification number: G11C11/1673 ,  G09C1/00 ,  G11C11/161 ,  H04L9/0866 ,  H04L9/30 ,  H04L9/3278

Abstract: One feature pertains to a method for implementing a physically unclonable function (PUF). The method includes providing an array of magnetoresistive random access memory (MRAM) cells, where the MRAM cells are each configured to represent one of a first logical state and a second logical state. The array of MRAM cells are un-annealed and free from exposure to an external magnetic field oriented in a direction configured to initialize the MRAM cells to a single logical state of the first and second logical states. Consequently, each MRAM cell has a random initial logical state of the first and second logical states. The method further includes sending a challenge to the MRAM cell array that reads logical states of select MRAM cells of the array, and obtaining a response to the challenge from the MRAM cell array that includes the logical states of the selected MRAM cells of the array.

Abstract translation: 一个特征涉及用于实现物理不可克隆功能（PUF）的方法。 该方法包括提供磁阻随机存取存储器（MRAM）单元阵列，其中MRAM单元被配置为表示第一逻辑状态和第二逻辑状态之一。 MRAM单元的阵列是未退火的，并且没有暴露于被配置为将MRAM单元初始化的方向定向到第一和第二逻辑状态的单个逻辑状态的外部磁场。 因此，每个MRAM单元具有第一和第二逻辑状态的随机初始逻辑状态。 该方法还包括向MRAM单元阵列发送挑战，该MRAM单元阵列读取阵列的选择MRAM单元的逻辑状态，以及从包括阵列的所选MRAM单元的逻辑状态的MRAM单元阵列获得对挑战的响应。

公开(公告)号：US09196334B2

公开(公告)日：2015-11-24

申请号：US13842122

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Seung H. Kang ,  Xiaochun Zhu

IPC: G11C11/16 ,  H01L43/02 ,  G06F12/08

CPC classification number: G11C11/161 ,  G06F12/0811 ,  G06F12/0893 ,  G06F12/0897 ,  G06F2212/2024 ,  G06F2212/222 ,  G11C11/1675 ,  G11C11/1693 ,  H01L43/02

Abstract: A hierarchical memory magnetoresistive random-access memory architecture is disclosed. In a particular embodiment, an apparatus includes a first magnetoresistive random-access memory (MRAM) device corresponding to a first level in a hierarchical memory system. The apparatus includes a second MRAM device corresponding to a second level in the hierarchical memory system. The first MRAM device has a first access latency and includes a first magnetic tunnel junction (MTJ) device having a first physical configuration. The second MRAM device has a second access latency and includes a second MTJ device having a second physical configuration. The first access latency is less than the second access latency.

Abstract translation: 公开了分层存储器磁阻随机存取存储器架构。 在特定实施例中，装置包括对应于分层存储器系统中的第一级的第一磁阻随机存取存储器（MRAM）装置。 该装置包括对应于分级存储器系统中的第二级的第二MRAM设备。 第一MRAM设备具有第一访问延迟并且包括具有第一物理配置的第一磁隧道结（MTJ）设备。 第二MRAM设备具有第二接入延迟并且包括具有第二物理配置的第二MTJ设备。 第一个访问延迟小于第二个访问延迟。

公开(公告)号：US20150070979A1

公开(公告)日：2015-03-12

申请号：US14072537

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G11C11/16

CPC classification number: G11C11/1695 ,  G09C1/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

Abstract: One feature pertains to a method of implementing a physically unclonable function. The method includes initializing an array of magnetoresistive random-access memory (MRAM) cells to a first logical state, where each of the MRAM cells have a random transition voltage that is greater than a first voltage and less than a second voltage. The transition voltage represents a voltage level that causes the MRAM cells to transition from the first logical state to a second logical state. The method further includes applying a programming signal voltage to each of the MRAM cells of the array to cause at least a portion of the MRAM cells of the array to randomly change state from the first logical state to the second logical state, where the programming signal voltage is greater than the first voltage and less than the second voltage.

Abstract translation: 一个特征涉及实现物理上不可克隆功能的方法。 该方法包括将磁阻随机存取存储器（MRAM）单元的阵列初始化为第一逻辑状态，其中每个MRAM单元具有大于第一电压且小于第二电压的随机转变电压。 转换电压表示使MRAM单元从第一逻辑状态转换到第二逻辑状态的电压电平。 该方法还包括将编程信号电压施加到阵列的每个MRAM单元，以使阵列的MRAM单元的至少一部分随机地将状态从第一逻辑状态改变到第二逻辑状态，其中编程信号 电压大于第一电压且小于第二电压。

公开(公告)号：US08889431B2

公开(公告)日：2014-11-18

申请号：US13683783

申请日：2012-11-21

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Matthew Nowak ,  Xia Li ,  Seung H. Kang

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3254 ,  H01F10/3272 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.

Abstract translation: 公开了磁隧道结（MTJ）及其形成方法。 被钉扎层设置在MTJ中，使得当提供在磁性随机存取存储器（MRAM）位单元中时，MTJ的自由层可以耦合到存取晶体管的漏极。 该结构改变写入电流流动方向，以使MTJ的写入电流特性与使用MTJ的MRAM位单元的写入电流供应能力对准。 结果，可以提供更多的写入电流以将MTJ从并行（P）切换到反并行（AP）状态。 在钉扎层上提供反铁磁材料（AFM）层以固定钉扎层的磁化强度。 为了提供足够的用于沉积AFM层以确保钉扎层磁化的区域，提供了具有大于自由层的自由层表面积的钉扎层表面积的钉扎层。

公开(公告)号：US08802452B2

公开(公告)日：2014-08-12

申请号：US13925953

申请日：2013-06-25

Applicant: Qualcomm Incorporated

Inventor： Xia Li ,  Seung H. Kang

IPC: H01L21/28

CPC classification number: G06F17/50 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming an MTJ cap layer on an MTJ structure and forming a top electrode layer coupled to the MTJ cap layer. The top electrode layer includes at least two layers and one layer of the two layers includes a nitrified metal.

Abstract translation: 在特定实施例中，形成磁性隧道结（MTJ）器件的方法包括在MTJ结构上形成MTJ覆盖层并形成耦合到MTJ覆盖层的顶部电极层。 顶部电极层包括至少两层，两层的一层包括硝化金属。

公开(公告)号：US20140210021A1

公开(公告)日：2014-07-31

申请号：US13749731

申请日：2013-01-25

Applicant: QUALCOMM INCORPORATED

Inventor： Xiaochun Zhu ,  Xia Li ,  Seung H. Kang

IPC: H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  G11C11/15 ,  G11C11/155 ,  G11C11/161 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: An in-process magnetic layer having an in-process area dimension is formed with a chemically damaged region at a periphery. At least a portion of the chemically damaged region is transformed to a chemically modified peripheral portion that is non-ferromagnetic. Optionally, the transforming is by oxidation, nitridation or fluorination, or combinations of the same.

Abstract translation: 具有处理区域尺寸的过程中的磁性层在周边形成化学损伤区域。 化学损伤区域的至少一部分被转化为非铁磁性的化学改性的周边部分。 任选地，转化是通过氧化，氮化或氟化，或其组合。

公开(公告)号：US08644063B2

公开(公告)日：2014-02-04

申请号：US13887492

申请日：2013-05-06

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung H. Kang

IPC: G11C11/15

CPC classification number: H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/307 ,  H01L27/222 ,  H01L43/08

Abstract: An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs).

Abstract translation: 电子器件制造工艺包括沉积底部电极层。 然后在底部电极层上制造电子器件。 底部电极层的图案化是在制造电子器件之后并且在单独的工艺中对图案化顶部电极进行的。 然后在电子器件上沉积第一电介质层，然后在底部电极层上沉积第一电介质层，然后是顶部电极层。 然后在与底部电极分离的工艺中对顶部电极进行图案化。 单独图案化顶部和底部电极通过减少电子器件之间的电介质材料中的空隙来提高产率。 一种电子设备，其制造工艺非常适用于磁隧道结（MTJ）。

公开(公告)号：US08614912B2

公开(公告)日：2013-12-24

申请号：US13869086

申请日：2013-04-24

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Taehyun Kim ,  Xia Li ,  Jung Pill Kim ,  Seung H. Kang

IPC: G11C11/14

CPC classification number: G11C5/025 ,  G11C5/08 ,  G11C11/165 ,  H01L27/0207 ,  Y10T29/49117

Abstract: A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.

Abstract translation: 大规模存储器阵列包括统一大小的虚拟位单元和有源位单元的均匀图案。 大规模存储器阵列中的子阵列由虚拟位单元分隔开。 信号分配电路形成为具有对应于虚拟位单元的宽度或高度的宽度或高度，使得信号分配电路占据与虚拟位单元相同的覆盖区，而不会破坏整个大规模阵列上的均匀图案。 类似大小或大于标准尺寸位单元的边缘虚拟单元可以放置在大规模阵列的边缘周围，以进一步减少图案负载影响。

公开(公告)号：US20130161771A1

公开(公告)日：2013-06-27

申请号：US13772576

申请日：2013-02-21

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Seung H. Kang ,  Xiaochun Zhu

IPC: H01L43/02 ,  G06F17/50

CPC classification number: H01L43/08 ,  G06F17/5068 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/12

Abstract: An apparatus includes a memory cell including a magnetic tunnel junction (MTJ) structure coupled between a bit line and a source line. The MTJ structure includes a free layer coupled to the bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. A physical dimension of the pinned layer produces an unbalanced offset magnetic field which corresponds to a first switching current of the MTJ structure that enables switching from the first state to the second state when a first voltage is applied to the bit line and corresponds to a second switching current that enables switching from the second state to the first state when the first voltage is applied to the source line.

Abstract translation: 一种装置包括存储单元，其包括耦合在位线和源极线之间的磁性隧道结（MTJ）结构。 MTJ结构包括耦合到位线和固定层的自由层。 自由层的磁矩基本上平行于处于第一状态的被钉扎层的磁矩，并且在第二状态下基本上与销钉层的磁矩反平行。 钉扎层的物理尺寸产生不平衡偏移磁场，其对应于MTJ结构的第一开关电流，当第一电压施加到位线并且对应于第二电压时，能够从第一状态切换到第二状态 当第一电压施加到源极线时，切换电流能够从第二状态切换到第一状态。