公开(公告)号：US20130023102A1

公开(公告)日：2013-01-24

申请号：US13415628

申请日：2012-03-08

申请人： Tomonori Aoyama ,  Kiyotaka Miyano ,  Hiroshi Nakazawa

发明人： Tomonori Aoyama ,  Kiyotaka Miyano ,  Hiroshi Nakazawa

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L21/823418 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/665 ,  H01L29/6659

摘要： According to one embodiment, a method of manufacturing a semiconductor device includes forming a gate electrode on a channel region in a silicon substrate via a gate insulation film; forming a source region and a drain region in the silicon substrate so as to sandwich the channel region along a channel direction by injecting desired impurities to the silicon substrate; forming amorphous regions containing the impurities on surfaces of the source region and the drain region by amorphousizing the surfaces of the source region and the drain region; forming nickel films on the amorphous regions; and forming crystal layers containing the activated impurities and forming nickel silicide films on the crystal layers at low temperature by radiating microwaves to the amorphous regions and the nickel films.

摘要翻译： 根据一个实施例，制造半导体器件的方法包括通过栅极绝缘膜在硅衬底的沟道区上形成栅电极; 在所述硅衬底中形成源极区域和漏极区域，以便通过将期望的杂质注入所述硅衬底而沿着沟道方向夹持所述沟道区域; 通过使源极区域和漏极区域的表面非晶化，在源区域和漏极区域的表面上形成含有杂质的非晶区域; 在非晶区上形成镍膜; 并且通过向非晶区域和镍膜辐射微波，形成含有活性杂质的晶体层，并在低温下在晶体层上形成硅化镍膜。

公开(公告)号：US08093141B2

公开(公告)日：2012-01-10

申请号：US12878780

申请日：2010-09-09

申请人： Tomonori Aoyama ,  Kiyotaka Miyano

发明人： Tomonori Aoyama ,  Kiyotaka Miyano

IPC分类号： H01L21/00

CPC分类号： H01L21/02532 ,  H01L21/02667 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/045

摘要： According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method can include forming an amorphous layer on a portion of a first silicon substrate having a first plane orientation, and irradiating with micro wave on the amorphous layer to transform from the amorphous layer into a crystalline layer having the first plane orientation.

摘要翻译： 根据一个实施例，公开了制造半导体器件的方法。 该方法可以包括在具有第一平面取向的第一硅衬底的一部分上形成非晶层，并且在非晶层上照射微波以从非晶层转变为具有第一平面取向的晶体层。

公开(公告)号：US20110076842A1

公开(公告)日：2011-03-31

申请号：US12894424

申请日：2010-09-30

申请人： Kenichi YOSHINO ,  Kiyotaka Miyano ,  Tomonori Aoyama

发明人： Kenichi YOSHINO ,  Kiyotaka Miyano ,  Tomonori Aoyama

IPC分类号： H01L21/26

CPC分类号： H01L29/6659 ,  H01L21/2686 ,  H01L21/324 ,  H01L29/7833

摘要： An ion implantation is performed to implant ions into a silicon substrate, and a microwave irradiation is performed to irradiate the silicon substrate with microwaves after the ion implantation. After the microwave irradiation, the silicon substrate is transferred to a heat-treatment apparatus, where the silicon substrate is treated with heat by being irradiated with light having a pulse width ranging from 0.1 milliseconds to 100 milliseconds, both inclusive.

摘要翻译： 执行离子注入以将离子注入到硅衬底中，并且在离子注入之后进行微波照射以对微硅进行照射。 在微波照射之后，将硅衬底转移到热处理装置中，其中通过用脉冲宽度为0.1毫秒至100毫秒的光照射硅衬底，其中热处理。

公开(公告)号：US07902030B2

公开(公告)日：2011-03-08

申请号：US12483728

申请日：2009-06-12

申请人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

发明人： Takayuki Ito ,  Yusuke Oshiki ,  Kouji Matsuo ,  Kenichi Yoshino ,  Takaharu Itani ,  Takuo Ohashi ,  Toshihiko Iinuma ,  Kiyotaka Miyano ,  Kunihiro Miyazaki

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/2686 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp(21541/T).

摘要翻译： 一种半导体装置的制造方法，其特征在于，在半导体基板的由第一原子构成的表面上形成有与半导体基板的表面的面积为5〜30％的开口率y的开口的开口部; 在所述开口中形成外延层，所述外延层由含有15〜25％的浓度的第二原子的混合晶体构成，所述第二原子的晶格常数不同于所述第一原子的晶格常数; 将杂质离子注入到外延层中; 并在预定温度T下进行活化退火，预定温度T等于或高于1150℃，并且满足y＆nlE; 1E-5exp（21541 / T）的关系。

公开(公告)号：US07416942B2

公开(公告)日：2008-08-26

申请号：US11708532

申请日：2007-02-21

申请人： Yukiteru Matsui ,  Shinichi Hirasawa ,  Atsushi Shigeta ,  Kiyotaka Miyano ,  Takeshi Nishioka ,  Hiroyuki Yano

发明人： Yukiteru Matsui ,  Shinichi Hirasawa ,  Atsushi Shigeta ,  Kiyotaka Miyano ,  Takeshi Nishioka ,  Hiroyuki Yano

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/461

CPC分类号： H01L27/11543 ,  C09G1/02 ,  H01L21/3212 ,  H01L21/7684 ,  H01L27/11526

摘要： A method for manufacturing a semiconductor device is provided. The method includes successively forming a first silicon film and a mask film above a semiconductor substrate through a gate insulating film, forming a plurality of trenches in the first silicon film and in the mask film to a depth to reach the semiconductor substrate, filling the plurality of trenches with the silicon oxide film, removing the mask film to expose the first silicon film existing between the silicon oxide films, selectively growing a second silicon film on the first silicon film, planarizing the second silicon film using an alkaline slurry exhibiting a pH of 13 or less and containing abrasive grains and a cationic surfactant, thereby obtaining a floating gate electrode film comprising the first and second silicon films, forming an interelectrode insulating film on the entire surface, and forming a control gate electrode film on the interelectrode insulating film.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括通过栅极绝缘膜在半导体衬底上连续地形成第一硅膜和掩模膜，在第一硅膜和掩模膜中形成多个沟槽到达半导体衬底的深度，填充多个 的沟槽，去除掩模膜以暴露存在于氧化硅膜之间的第一硅膜，选择性地生长第一硅膜上的第二硅膜，使用表现出pH为 13以下，含有磨粒和阳离子性表面活性剂，从而得到包含第一和第二硅膜的浮栅电极膜，在整个表面上形成电极间绝缘膜，并在电极间绝缘膜上形成控制栅极电极膜。

公开(公告)号：US20080102616A1

公开(公告)日：2008-05-01

申请号：US11999958

申请日：2007-12-07

申请人： Yoshitaka Tsunashima ,  Seiji Ihumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

发明人： Yoshitaka Tsunashima ,  Seiji Ihumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

IPC分类号： H01L21/283

CPC分类号： H01L21/82345 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31604 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

摘要： Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

摘要翻译： 权利要求和公开的是一种半导体器件，包括具有在包含金属，硅和氧的金属硅酸盐的化合物中含有氮或氟的栅极绝缘膜结构的晶体管，具有非晶态金属氧化物层叠结构的栅极绝缘膜结构 膜和金属硅酸盐膜，或具有包括第一金属元素的氧化物膜的第一栅极绝缘膜和包括第二金属元素的金属硅酸盐膜的第二栅极绝缘膜的栅极绝缘膜结构。

公开(公告)号：US07361960B1

公开(公告)日：2008-04-22

申请号：US09688989

申请日：2000-10-17

申请人： Yoshitaka Tsunashima ,  Kiyotaka Miyano ,  Yukihiro Ushiku

发明人： Yoshitaka Tsunashima ,  Kiyotaka Miyano ,  Yukihiro Ushiku

IPC分类号： H01L29/76 ,  H01L31/00

CPC分类号： H01L27/11502 ,  H01L21/76224 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823475 ,  H01L27/10873 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534 ,  H01L29/78391 ,  Y10S257/903

摘要： A first insulator film and a first polysilicon film are formed on first and second element regions of a semiconductor substrate. The first insulator film and first polysilicon film are removed from the second element region. A second insulator film is formed on the second element region from which the first insulator film and first polysilicon film are removed, and a second polysilicon film is formed on the second insulator film. The first polysilicon film is processed, forming a first gate electrode at the first element region. The second polysilicon film is processed, forming a second gate electrode at the second element region. A silicon nitride film is removed from an element-isolation region. A metal film is formed on the region from which the silicon nitride film has been removed, and connects the first and second gate electrodes.

摘要翻译： 第一绝缘膜和第一多晶硅膜形成在半导体衬底的第一和第二元件区上。 从第二元件区域去除第一绝缘膜和第一多晶硅膜。 在除去第一绝缘膜和第一多晶硅膜的第二元件区域上形成第二绝缘膜，在第二绝缘膜上形成第二多晶硅膜。 处理第一多晶硅膜，在第一元件区域形成第一栅电极。 处理第二多晶硅膜，在第二元件区域形成第二栅电极。 从元件隔离区域去除氮化硅膜。 在去除了氮化硅膜的区域上形成金属膜，并且连接第一和第二栅电极。

公开(公告)号：US07235469B2

公开(公告)日：2007-06-26

申请号：US10998193

申请日：2004-11-29

申请人： Yasunori Okayama ,  Kiyotaka Miyano ,  Kazunari Ishimaru

发明人： Yasunori Okayama ,  Kiyotaka Miyano ,  Kazunari Ishimaru

IPC分类号： H01L21/26

CPC分类号： H01L29/4232 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665

摘要： A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is higher near an interface to the insulator and lower in a surface side opposite to the insulator, and a second gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is substantially uniform and an n-type dopant of a concentration of above 6×1020 atoms/cm3 is contained.

摘要翻译： 适用于小型化并且包括适当控制的Si / SiGe栅电极的半导体器件包括形成在半导体衬底上的绝缘体，形成在绝缘体上并包括硅 - 锗的第一栅电极，其中锗浓度在与 绝缘体，并且在与绝缘体相对的表面侧下方，以及形成在绝缘体上并包括硅锗的第二栅电极，其中锗浓度基本上均匀，并且浓度高于6×10 20的n型掺杂剂 原子/ cm 3含有。

公开(公告)号：US20070111433A1

公开(公告)日：2007-05-17

申请号：US11594726

申请日：2006-11-09

申请人： Shinichi Hirasawa ,  Atsushi Shigeta ,  Kiyotaka Miyano ,  Yukiteru Matsui ,  Takeshi Nishioka ,  Hiroyuki Yano

发明人： Shinichi Hirasawa ,  Atsushi Shigeta ,  Kiyotaka Miyano ,  Yukiteru Matsui ,  Takeshi Nishioka ,  Hiroyuki Yano

IPC分类号： H01L21/8242

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/40114 ,  H01L29/66825

摘要： A method for manufacturing a semiconductor device comprises forming a first silicon layer above a semiconductor substrate; forming a stopper layer on said first silicon layer; partially removing said stopper layer and said first silicon layer above said semiconductor substrate to form a plurality of trenches; forming an insulating layer on said stopper layer with inside of said trenches; partially removing said insulating layer to expose said stopper layer; after partially removing said insulating layer, removing said stopper layer to expose said first silicon layer; selectively growing second silicon layer on said exposed first silicon layer; nonselectively growing a third silicon layer on said second silicon layer; and polishing at least a surface of said third silicon layer by performing chemical mechanical polishing.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成第一硅层; 在所述第一硅层上形成阻挡层; 部分地去除所述半导体衬底之上的所述阻挡层和所述第一硅层以形成多个沟槽; 在所述沟槽的内部在所述阻挡层上形成绝缘层; 部分地去除所述绝缘层以暴露所述阻挡层; 在部分地去除所述绝缘层之后，去除所述阻挡层以露出所述第一硅层; 在所述暴露的第一硅层上选择性地生长第二硅层; 在所述第二硅层上非选择地生长第三硅层; 以及通过进行化学机械抛光来抛光所述第三硅层的至少一个表面。

公开(公告)号：US20060194405A1

公开(公告)日：2006-08-31

申请号：US11266262

申请日：2005-11-04

申请人： Hajime Nagano ,  Kiyotaka Miyano ,  Osamu Arisumi

发明人： Hajime Nagano ,  Kiyotaka Miyano ,  Osamu Arisumi

IPC分类号： H01L21/76 ,  H01L29/00

CPC分类号： H01L21/823481 ,  H01L21/76224

摘要： A semiconductor device has an element isolating region formed of an insulating film having etching rates different from each other in a side close to an inside wall and a center side of a trench formed on a semiconductor substrate, and a selective epitaxial layer formed in both sides of the element isolating region, wherein the element isolating region has a tip portion in a tapered shape or a stepwise shape of which a width becomes narrower at a side closer to the tip portion.

摘要翻译： 半导体器件具有由绝缘膜形成的元件隔离区，该绝缘膜具有在靠近半导体衬底上形成的沟槽的内壁和中心侧的蚀刻速率彼此不同的蚀刻速率，以及形成在两侧的选择性外延层 所述元件隔离区域具有锥形形状的尖端部分或在靠近所述尖端部分的一侧宽度变窄的阶梯形状。