公开(公告)号：US07337280B2

公开(公告)日：2008-02-26

申请号：US11055301

申请日：2005-02-10

申请人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

发明人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542

摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

摘要翻译： 一种用于在具有上部存储器和下部存储器高速缓存的存储器层级的数据处理系统中的高速缓存管理的系统和方法。 较低的存储器高速缓存控制器访问一致性状态表以确定当从上部存储器高速缓存中的一个接收到转入请求时存在于下部存储器高速缓存中的高速缓存行的一致性状态的替换策略。 一致性状态表实现替换策略，其在从上部存储器高速缓存中拔出时，在包含在两个级别的存储器中的特定高速缓存行的上下存储器高速缓存之间保留更有价值的高速缓存一致性状态信息。

公开(公告)号：US07200717B2

公开(公告)日：2007-04-03

申请号：US10965144

申请日：2004-10-14

申请人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3851 ,  G06F12/0855

摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit coupled to the instruction sequencing unit that concurrently executes multiple threads of instructions. The processor core, responsive to the at least one instruction execution unit executing a load-reserve instruction in a first thread that binds to a load target address in the store-through upper level cache during a reservation hazard window associated with a conflicting store-conditional operation of a second thread, causes a subsequent store-conditional operation of the first thread to a store target address matching the load target address to fail if the store-conditional operation of the second thread succeeds.

摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括处理器核心，该处理器核心包括通过存储的上级高速缓存，指令执行指令排序单元，数据寄存器以及耦合到指令排序单元的至少一个指令执行单元， 同时执行多个指令线程。 所述处理器核心响应于所述至少一个指令执行单元在与冲突存储条件相关联的预留危险窗口期间执行在所述存储通过上级高速缓存中的绑定到加载目标地址的第一线程中的加载保留指令 如果第二线程的存储条件操作成功，则第二线程的操作使得第一线程的后续存储条件操作到与加载目标地址匹配的存储目标地址失败。

公开(公告)号：US07047320B2

公开(公告)日：2006-05-16

申请号：US10339724

申请日：2003-01-09

申请人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F3/00

CPC分类号： G06F13/124 ,  G06F12/0835

摘要： An integrated circuit, such as a processing unit, includes a substrate and integrated circuitry formed in the substrate. The integrated circuitry includes a processor core that executes instructions, an interconnect interface, coupled to the processor core, that supports communication between the processor core and a system interconnect external to the integrated circuit, and at least a portion of an external communication adapter, coupled to the processor core, that supports input/output communication via an input/output communication link.

摘要翻译： 诸如处理单元的集成电路包括衬底和形成在衬底中的集成电路。 集成电路包括执行指令的处理器核心，耦合到处理器核心的互连接口，其支持处理器核心与集成电路外部的系统互连之间的通信，以及外部通信适配器的至少一部分，耦合 通过输入/输出通信链路支持输入/输出通信的处理器核心。

公开(公告)号：US06629214B1

公开(公告)日：2003-09-30

申请号：US09437186

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1300

CPC分类号： G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857

摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized. In particular, the claimed system and method provides that a given processor, after acquiring a lock or reservation to a given cache line, will keep the lock, to make successive modifications to the cache line, instead of releasing it to other processors after making only one modification. By doing so, the overhead typically required to acquire a lock before making any cache line modification is eliminated for successive modifications.

摘要翻译： 多处理器数据处理系统需要仔细管理以保持高速缓存一致性。 使用MESI方法的传统系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。 所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。 额外的缓存状态允许优化缓存状态转换序列。 特别地，所要求保护的系统和方法规定，给定的处理器在获得对给定高速缓存行的锁定或预留之后将保持锁定以对缓存行进行连续修改，而不是在仅进行制作之后将其释放到其他处理器 一个修改。 通过这样做，为了连续修改，消除了在进行任何高速缓存行修改之前获取锁的通常需要的开销。

公开(公告)号：US06487637B1

公开(公告)日：2002-11-26

申请号：US09364408

申请日：1999-07-30

申请人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1300

CPC分类号： G06F9/30047 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3842 ,  G06F12/0897

摘要： A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. These prefetch requests can be demand load requests, where the processing unit will need the operand data or instructions, or speculative load requests, where the processing unit may or may not need the operand data or instructions, but a branch prediction or stream association predicts that they might be needed. Further branch predictions or stream associations that were made based on an earlier speculative choice are linked by using a tag pool which assigns a bit fields in the tag pool entries to the level of speculation depth. Each entry shares in common the bit field values associated with earlier branches or stream associations. When a branch or stream predicted entry is no longer needed, that entry can be cancelled and all entries that were to be loaded dependent on that entry can likewise be cancelled by walking through all entries sharing the bit fields corresponding to the speculation depth of the cancelled entry and tagging those entries as invalid.

摘要翻译： 一种操作计算机系统的多级存储器层级的方法和体现该方法的装置，其中指令从直接从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。 本发明适用于作为操作数数据或指令的值。 这些预取请求可以是需求负载请求，其中处理单元将需要操作数数据或指令或推测性负载请求，其中处理单元可能需要或可能不需要操作数数据或指令，但分支预测或流关联预测 他们可能需要。 通过使用将标签池条目中的位字段分配给投机深度的标签池来链接根据较早的推测选择进行的进一步分支预测或流关联。 每个条目共享与早期分支或流关联相关联的比特字段值。 当不再需要分支或流预测条目时，可以取消该条目，并且可以通过遍历与所取消的投机深度相对应的比特字段的所有条目，来取消根据该条目加载的所有条目 输入并标记这些条目为无效。

公开(公告)号：US06438656B1

公开(公告)日：2002-08-20

申请号：US09364574

申请日：1999-07-30

申请人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1200

CPC分类号： G06F9/3804 ,  G06F9/30047 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3861 ,  G06F12/0862 ,  G06F12/0897

摘要： A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. These prefetch requests can be demand load requests, where the processing unit will need the operand data or instructions, or speculative load requests, where the processing unit may or may not need the operand data or instructions, but a branch prediction or stream association predicts that they might be needed. After a predetermined number of cycles has elapsed, the speculative load request is cancelled if the request has not already been completed.

摘要翻译： 一种操作计算机系统的多级存储器层级的方法和体现该方法的装置，其中指令从直接从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。 本发明适用于作为操作数数据或指令的值。 在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别 存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。 这些预取请求可以是需求负载请求，其中处理单元将需要操作数数据或指令或推测性负载请求，其中处理单元可能需要或可能不需要操作数数据或指令，但分支预测或流关联预测 他们可能需要。 在经过预定数量的周期之后，如果请求尚未完成，则推测加载请求被取消。

公开(公告)号：US06345344B1

公开(公告)日：2002-02-05

申请号：US09437181

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1200

CPC分类号： G06F12/126 ,  G06F12/0831

摘要： A novel cache coherency protocol provides a modified-unsolicited (Mu) cache state to indicate that a value held in 5 a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the Mu state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The Mu state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the Mu state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

摘要翻译： 一种新颖的高速缓存一致性协议提供修改后的未经请求（Mu）高速缓存状态，以指示缓存行5中保存的值已经被修改（即当前与系统存储器不一致），但是被另一个处理单元修改 通过与当前包含Mu状态的值的高速缓存相关联的处理单元，并且该值被保持为排除任何其他水平相邻的高速缓存。 因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。 作为对读取请求的窥探响应的结果，可以应用Mu状态。 读取请求可以包括用于指示请求的高速缓存能够利用Mu状态的标志。 或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

公开(公告)号：US08433851B2

公开(公告)日：2013-04-30

申请号：US11839663

申请日：2007-08-16

申请人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

发明人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0851 ,  G06F12/0864

摘要： A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

摘要翻译： 一种方法和计算机系统，用于通过重新配置扇区到片分配和较低的高速缓存寻址方案来减少具有扇区和分片的低级高速缓存的高速缓存子系统中的布线拥塞，所需的房地产和访问延迟。 通过这种分配，具有不连续地址的扇区被放置在相同的片内，并且基于对高速缓存片内的可寻址扇区的这种重新分配，可以在两级低级高速缓存之间进行简化布线方案。 此外，低速缓存有效地址标签被重新配置，使得先前分配用于识别扇区和片的地址字段相对于地址标签内的彼此的位置被切换。 地址位的这种重新分配使得能够基于指示的扇区进行直接片寻址。

公开(公告)号：US08281075B2

公开(公告)日：2012-10-02

申请号：US12423355

申请日：2009-04-14

申请人： Lakshminarayana Baba Arimilli ,  Brian Mitchell Bass ,  David Wayne Cummings ,  Bernard Charles Drerup ,  Guy Lynn Guthrie ,  Ronald Nick Kalla ,  Hugh Shen ,  Michael Steven Siegel ,  William John Starke ,  Derek Edward Williams

发明人： Lakshminarayana Baba Arimilli ,  Brian Mitchell Bass ,  David Wayne Cummings ,  Bernard Charles Drerup ,  Guy Lynn Guthrie ,  Ronald Nick Kalla ,  Hugh Shen ,  Michael Steven Siegel ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F13/00 ,  G06F13/36 ,  G06F13/38 ,  G06F9/315

CPC分类号： G06F12/1458 ,  G06F9/30047 ,  G06F9/30087 ,  G06F12/0893

摘要： A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command process the specific request-type command when the core permission controls are the same as the respective slave permission controls. The trusted kernel may be included in a hypervisor or an operating system.

摘要翻译： 用户代码触发系统总线写命令的技术包括识别用户指令序列中的特定存储型指令。 特定存储型指令被转换成特定的请求类型命令，其被配置为包括核心权限控制（存储在可信内核中的处理器核心的核心配置寄存器中）和用户创建的数据（存储在高速缓存中） 记忆）。 从设备通过具有相应从属权限控制的寄存器空间（可由可信内核访问）进行配置。 然后，经由系统总线从高速缓冲存储器发送特定的请求类型命令。 在这种情况下，当核心权限控制与相应从属许可控制相同时，接收特定请求类型命令的从设备处理特定请求类型命令。 可信内核可能包含在管理程序或操作系统中。

公开(公告)号：US07849298B2

公开(公告)日：2010-12-07

申请号：US12352462

申请日：2009-01-12

申请人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30123 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/462

摘要： A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

摘要翻译： 公开了一种方法和系统，用于在接收到处理器的处理中断时，保存对于在处理器中执行处理不重要的软​​状态信息。 软状态经由存储器接口传送到与处理器相关联的存储器。 优选地，软状态在处理器内经由处理器内的扫描链路径在处理器内传送到存储器接口，这允许功能数据路径通过软状态的存储而保持不受阻碍。 此后，当再次执行处理时，可以从存储器恢复存储的软状态。