公开(公告)号：US06507931B2

公开(公告)日：2003-01-14

申请号：US09892572

申请日：2001-06-28

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

IPC分类号： G06F1750

CPC分类号： G06F17/5081

摘要： A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.

公开(公告)号：US06245466B1

公开(公告)日：2001-06-12

申请号：US09358769

申请日：1999-07-22

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

IPC分类号： G03F900

CPC分类号： G03F1/36

摘要： A rectangular supplemental pattern having two edges of dimensions s1 and s2 is added to a main pattern corresponding to a design pattern. Where a change amount of shortening with respect to small changes &Dgr;s1 and &Dgr;s2 of the plan shape of the supplemental pattern, the plan shape of the supplemental pattern is determined such that the change amount s′={(±&Dgr;x/±&Dgr;s1)2+(±&Dgr;x/±&Dgr;s1)2}½ of the pattern plan shape on a wafer after transfer becomes a predetermined value or less.

摘要翻译： 将具有尺寸s1和s2的两个边缘的矩形补充图案添加到对应于设计图案的主图案。 在对补充模式的计划形状的小变化DELTAs1和DELTA2进行缩短的变化量的情况下，确定补充模式的计划形状，使得变化量s'= {（±DELTAx /±DELTAs1）2+ 转印后的晶片上的图形平面形状的（±DELTAx /±DELTAs1）2} 1/2成为规定值以下。

公开(公告)号：US06221539B1

公开(公告)日：2001-04-24

申请号：US09358824

申请日：1999-07-22

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

IPC分类号： G03F900

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： All edge positions constituting a first mask pattern are shifted by a predetermined change amount, to obtain a second mask pattern. A first finished plan shape transferred by the fist mask pattern and a second finished plan shape transferred by the second mask pattern are obtained by a calculation. Coefficients, which are obtained by respectively dividing dimensional differences between the edge positions of the first and second finished plan shapes by the change amount, are respectively calculated and assigned for edges. A corrected pattern is prepared by shifting the edge positions of the first mask pattern in accordance with magnitude of division of differences between a design pattern and the first finished plan shape by the coefficients assigned to the edges.

摘要翻译： 构成第一掩模图案的所有边缘位置偏移预定的变化量，以获得第二掩模图案。 通过计算获得通过第一掩模图案传送的第一完成平面形状和通过第二掩模图案传送的第二完成平面形状。 通过分别计算第一和第二完成平面形状的边缘位置之间的尺寸差异所得到的系数，并分配给边缘。 通过根据分配给边缘的系数，根据设计图案和第一完成平面形状之间的差分的大小来移动第一掩模图案的边缘位置来准备校正图案。

公开(公告)号：US09207531B2

公开(公告)日：2015-12-08

申请号：US13239449

申请日：2011-09-22

申请人： Hiroko Nakamura ,  Koji Asakawa ,  Shigeki Hattori ,  Satoshi Tanaka ,  Toshiya Kotani

发明人： Hiroko Nakamura ,  Koji Asakawa ,  Shigeki Hattori ,  Satoshi Tanaka ,  Toshiya Kotani

IPC分类号： H01L21/31 ,  H01L21/469 ,  G03F7/00 ,  B81C1/00 ,  B82Y10/00 ,  B82Y40/00

CPC分类号： G03F7/0002 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y40/00

摘要： According to one embodiment, a pattern including first and second block phases is formed by self-assembling a block copolymer onto a film to be processed. The entire block copolymer present in a first region is removed under a first condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in a region other than the first region. The first block phase present in a second region is selectively removed under a second condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in an overlap region between a region other than the first region and a region other than the second region, and leaving a pattern of second block phase in the second region excluding the overlap region. The film is etched with the left patterns as masks.

摘要翻译： 根据一个实施方案，通过将嵌段共聚物自组装成待加工的膜来形成包括第一和第二嵌段相的图案。 存在于第一区域中的整个嵌段共聚物在第一条件下通过进行能量束照射和显影而除去，从而在第一区域以外的区域留下包括第一和第二嵌段相的图案。 存在于第二区域中的第一块相位通过进行能量束照射和显影而在第二条件下被选择性地去除，从而在包括第一区域和第一区域之间的重叠区域中留下包括第一和第二块相的图案， 区域，并且在除了重叠区域之外的第二区域中留下第二块相位的图案。 用左图案蚀刻该胶片作为掩模。

公开(公告)号：US20130241073A1

公开(公告)日：2013-09-19

申请号：US13614217

申请日：2012-09-13

申请人： Takaki Hashimoto ,  Yasunobu Kai ,  Toshiya Kotani

发明人： Takaki Hashimoto ,  Yasunobu Kai ,  Toshiya Kotani

IPC分类号： H01L23/528 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/768 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76895 ,  H01L27/11519 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality at first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires.

摘要翻译： 根据一个实施例，半导体器件包括以预定间距平行布置的多条导线，多个第一触点分别连接到导线之间的奇数编号，并且与正交方向平行布置，与 与导线的布线方向相连接的多个第二触点，以及多个第二触点，每个第二触点各自连接到电线中的偶数线，并且相对于线的布线方向在正交方向上平行布置， 在与导线的布线方向正交的方向上的第一触点相对于第二触点偏离线的间距的方式偏离布线方向的第一触点。

公开(公告)号：US08443310B2

公开(公告)日：2013-05-14

申请号：US13237435

申请日：2011-09-20

申请人： Masanari Kajiwara ,  Toshiya Kotani ,  Sachiko Kobayashi ,  Hiromitsu Mashita ,  Fumiharu Nakajima

发明人： Masanari Kajiwara ,  Toshiya Kotani ,  Sachiko Kobayashi ,  Hiromitsu Mashita ,  Fumiharu Nakajima

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F1/70 ,  G03F7/70441

摘要： A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area.

摘要翻译： 实施例的图案校正方法在形成有衬底图案的情况下，在成为误差图案的位置附近的电路图案的设计布局上计算图案覆盖率的分布。 然后，通过添加加法图案，设置图案覆盖物的分布差异变小的设计布局上的区域作为附加区域。 接下来，生成要添加到相加区域的添加模式候选，并根据预定的选择标准从候选中选择要添加到设计布局的添加模式，并将添加模式添加到添加区域。

公开(公告)号：US08347241B2

公开(公告)日：2013-01-01

申请号：US12354119

申请日：2009-01-15

申请人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Chikaaki Kodama

发明人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Chikaaki Kodama

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： A pattern generation method includes: acquiring a first design constraint for first patterns to be formed on a process target film by a first process, the first design constraint using, as indices, a pattern width of an arbitrary one of the first patterns, and a space between the arbitrary pattern and a pattern adjacent to the arbitrary pattern; correcting the first design constraint in accordance with pattern conversion by the second process, and thereby acquiring a second design constraint for the second pattern which uses, as indices, two patterns on both sides of a predetermined pattern space of the second pattern; judging whether the design pattern fulfils the second design constraint; and changing the design pattern so as to correspond to a value allowed by the second design constraint when the design constraint is not fulfilled.

摘要翻译： 图案生成方法包括：通过第一处理获取要在过程目标胶片上形成的第一图案的第一设计约束，所述第一设计约束使用作为所述第一图案中的任意一个的图案宽度的索引，以及 任意图案之间的空间和与任意图案相邻的图案; 根据第二处理的图案转换来校正第一设计约束，从而获得第二图案的第二设计约束，该第二图案使用在第二图案的预定图案空间的两侧上的两个图案作为索引; 判断设计模式是否符合第二设计约束; 并且当不满足设计约束时，改变设计模式以对应于由第二设计约束允许的值。

公开(公告)号：US20120070985A1

公开(公告)日：2012-03-22

申请号：US13233971

申请日：2011-09-15

申请人： Takaki Hashimoto ,  Kazuya Fukuhara ,  Toshiya Kotani ,  Yasunobu Kai

发明人： Takaki Hashimoto ,  Kazuya Fukuhara ,  Toshiya Kotani ,  Yasunobu Kai

IPC分类号： H01L21/768 ,  G03B27/32

CPC分类号： H01L27/0207 ,  G03F1/50 ,  G03F7/70325 ,  H01L21/0274 ,  H01L21/31144 ,  H01L27/11519 ,  H01L27/11524

摘要： According to one embodiment, an exposure method is disclosed. The method can include applying light to a photomask by an illumination. The method can include converging diffracted beams emitted from the photomask by a lens. In addition, the method can include imaging a plurality of point images on an exposure surface. On the photomask, a light transmitting region is formed at a lattice point represented by nonorthogonal unit cell vectors, and in the illumination, a light emitting region is set so that three or more of the diffracted beams pass through positions equidistant from center of a pupil of the lens.

摘要翻译： 根据一个实施例，公开了曝光方法。 该方法可以包括通过照明将光照射到光掩模。 该方法可以包括通过透镜会聚从光掩模发射的衍射光束。 此外，该方法可以包括在曝光表面上成像多个点图像。 在光掩模上，在由非正交单元矢量表示的格点处形成光透射区域，在照明中，设定发光区域，使得三个以上的衍射光束通过与瞳孔中心等距的位置 的镜头。

公开(公告)号：US08122385B2

公开(公告)日：2012-02-21

申请号：US12129167

申请日：2008-05-29

申请人： Kazuya Fukuhara ,  Tatsuhiko Higashiki ,  Toshiya Kotani ,  Satoshi Tanaka ,  Takashi Sato ,  Akiko Mimotogi ,  Masaki Satake

发明人： Kazuya Fukuhara ,  Tatsuhiko Higashiki ,  Toshiya Kotani ,  Satoshi Tanaka ,  Takashi Sato ,  Akiko Mimotogi ,  Masaki Satake

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： In a model-based OPC which makes a suitable mask correction for each mask pattern using an optical image intensity simulator, a mask pattern is divided into subregions and the model of optical image intensity simulation is changed according to the contents of the pattern in each subregion. When the minimum dimensions of the mask pattern are smaller than a specific threshold value set near the exposure wavelength, the region is calculated using a high-accuracy model and the other regions are calculated using a high-speed model.

摘要翻译： 在基于模型的OPC中，使用光学图像强度模拟器对每个掩模图案进行适当的掩模校正，将掩模图案划分为子区域，并且根据每个子区域中的图案的内容来改变光学图像强度模拟模型 。 当掩模图案的最小尺寸小于在曝光波长附近设置的特定阈值时，使用高精度模型计算该区域，并且使用高速模型来计算其它区域。

公开(公告)号：US08065637B2

公开(公告)日：2011-11-22

申请号：US12267465

申请日：2008-11-07

申请人： Toshiya Kotani

发明人： Toshiya Kotani

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  H01J2237/31769

摘要： A semiconductor device having a physical pattern based on a designed pattern is provided. The designed pattern includes a target pattern and a correction pattern. The target pattern includes a first portion of an edge with a first distance between the first portion and a pattern opposed thereto, a second portion of the edge with a second distance between the second portion and a pattern opposed thereto, which is different from the first distance, and a third portion of the edge having a first region of the edge with the first distance between the first region and the pattern opposed thereto.

摘要翻译： 提供具有基于设计图案的物理图案的半导体器件。 设计的图案包括目标图案和校正图案。 目标图案包括边缘的第一部分，第一部分与第一部分和与其相对的图案具有第一距离，边缘的第二部分在第二部分和与其相对的图案之间具有第二距离，该第二部分与第一部分不同于第一部分 所述边缘的第三部分具有所述边缘的第一区域，所述第一区域在所述第一区域和与其相对的图案之间具有第一距离。