公开(公告)号：US10797061B2

公开(公告)日：2020-10-06

申请号：US16221942

申请日：2018-12-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akio Nishida ,  Toshihiro Iizuka ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Fei Zhou ,  Srikanth Ranganathan

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L29/08 ,  H01L29/10 ,  H01L21/324 ,  H01L27/11565 ,  H01L21/8239 ,  H01L21/8234 ,  H01L27/11573 ,  H01L27/11529

Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel. Vertical tensile stress can be induced by using a layer stack including polysilicon and a silicon-germanium alloy for the vertical semiconductor channel.

公开(公告)号：US10790300B2

公开(公告)日：2020-09-29

申请号：US16290277

申请日：2019-03-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou ,  Rahul Sharangpani

IPC: H01L21/00 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.

公开(公告)号：US20200243500A1

公开(公告)日：2020-07-30

申请号：US16848137

申请日：2020-04-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Rahul Sharangpani

IPC: H01L25/18 ,  G11C16/26 ,  H01L25/00 ,  H01L23/00 ,  G11C16/08 ,  H01L23/48 ,  G11C16/30 ,  H01L27/11582 ,  H01L27/11556 ,  G11C16/24

Abstract: A support die includes complementary metal-oxide-semiconductor (CMOS) devices, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry. A first memory die including a first three-dimensional array of memory elements is bonded to the support die. First memory-die bonding pads of the first memory die are bonded to the front support-die bonding pads. A second memory die including a second three-dimensional array of memory elements is bonded to the support die. Second memory-die bonding pads of the second memory die are bonded to the backside bonding structures.

公开(公告)号：US10707233B1

公开(公告)日：2020-07-07

申请号：US16362857

申请日：2019-03-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Fei Zhou ,  Raghuveer S. Makala

IPC: H01L27/11582 ,  H01L21/3105 ,  H01L27/1157 ,  H01L27/11524 ,  H01L23/528 ,  H01L23/532 ,  H01L29/08 ,  H01L23/522 ,  H01L21/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/11556

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.

公开(公告)号：US10665581B1

公开(公告)日：2020-05-26

申请号：US16255413

申请日：2019-01-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Rahul Sharangpani

IPC: G11C5/04 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L23/48

Abstract: A support die includes complementary metal-oxide-semiconductor (CMOS) devices, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry. A first memory die including a first three-dimensional array of memory elements is bonded to the support die. First memory-die bonding pads of the first memory die are bonded to the front support-die bonding pads. A second memory die including a second three-dimensional array of memory elements is bonded to the support die. Second memory-die bonding pads of the second memory die are bonded to the backside bonding structures.

公开(公告)号：US10361213B2

公开(公告)日：2019-07-23

申请号：US15483862

申请日：2017-04-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Fumitaka Amano ,  Raghuveer S. Makala ,  Fei Zhou ,  Keerti Shukla

IPC: H01L27/11524 ,  H01L23/532 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/792

Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.

公开(公告)号：US10050054B2

公开(公告)日：2018-08-14

申请号：US15286063

申请日：2016-10-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Johann Alsmeier ,  Raghuveer S. Makala ,  Senaka Kanakamedala ,  Rahul Sharangpani ,  James Kai

IPC: H01L21/768 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556

Abstract: A layer stack including an alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of memory stack structures, backside trenches are formed through the layer stack. The sacrificial material layers are replaced with electrically conductive layers. Drain select level dielectric isolation structures are formed through drain select level of the stack after formation of the electrically conductive layers. The drain select level dielectric isolation structures laterally separate portions of conductive layers that are employed as drain select level gate electrodes for the memory stack structures.

公开(公告)号：US12217965B2

公开(公告)日：2025-02-04

申请号：US17573429

申请日：2022-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Yujin Terasawa ,  Naoki Takeguchi ,  Kensuke Yamaguchi ,  Masaaki Higashitani

IPC: H01L21/285 ,  C23C16/14 ,  C23C16/455 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27 ,  H10B51/20 ,  H10B63/00

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

公开(公告)号：US12176203B2

公开(公告)日：2024-12-24

申请号：US17573452

申请日：2022-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Yujin Terasawa ,  Naoki Takeguchi ,  Kensuke Yamaguchi ,  Masaaki Higashitani

IPC: H01L21/02 ,  C23C16/458

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

公开(公告)号：US12137554B2

公开(公告)日：2024-11-05

申请号：US17525233

申请日：2021-11-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou

IPC: H10B41/27 ,  H01L21/768 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, etch stop plates located in the staircase region, laterally and vertically spaced apart among one another, and overlying an end portion of a respective one of the electrically conductive layers, and contact via structures located in a staircase region, vertically extending through a respective one of the etch stop plates, and contacting a respective one of the electrically conductive layers.