公开(公告)号：US10957577B2

公开(公告)日：2021-03-23

申请号：US16301276

申请日：2017-05-17

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L21/00 ,  H01L21/762

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

公开(公告)号：US20190181035A1

公开(公告)日：2019-06-13

申请号：US16301260

申请日：2017-05-17

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76254 ,  H01L27/1203

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.

公开(公告)号：US09698063B2

公开(公告)日：2017-07-04

申请号：US14381537

申请日：2013-02-18

Applicant: Soitec

Inventor： Patrick Reynaud ,  Walter Schwarzenbach ,  Konstantin Bourdelle ,  Jean-Francois Gilbert

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L22/14 ,  G01R31/2601 ,  H01L22/20

Abstract: The invention concerns a method of testing a semiconductor-on-insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor-on-insulator type structures including carrying out the test on a sample structure from the batch.

公开(公告)号：US09190284B2

公开(公告)日：2015-11-17

申请号：US14397287

申请日：2013-05-01

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Carine Duret ,  Francois Boedt

IPC: H01L21/306 ,  H01L21/66 ,  H01L21/762

CPC classification number: H01L21/30604 ,  H01L21/76251 ,  H01L22/12 ,  H01L22/20

Abstract: The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, the semiconductor layer being covered with a sacrificial oxide layer, comprising measuring, at a plurality of points distributed over the surface of the structure, the thickness of the sacrificial oxide layer and of the semiconductor layer, so as to produce a mapping of the thickness of the semiconductor layer and to determine, from the measurements, the average thickness of the semiconductor layer, selective etching of the sacrificial oxide layer so as to expose the semiconductor layer, and carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer, so as to thin, at least locally, the semiconductor layer by a thickness identified as being an overthickness at the end of the measurement step.

Abstract translation: 本发明涉及一种用于处理绝缘体上半导体结构的方法，该方法连续地包括一个具有小于或等于100nm的厚度的支撑衬底，电介质层和半导体层，半导体层被牺牲 氧化物层，包括在分布在结构表面上的多个点处测量牺牲氧化物层和半导体层的厚度，以便产生半导体层的厚度的映射，并且从 测量，半导体层的平均厚度，牺牲氧化物层的选择性蚀刻以暴露半导体层，并且对半导体层进行化学蚀刻，其应用，温度和/或持续时间条件被调整 作为半导体层的映射和/或平均厚度的函数，从而至少局部地薄化半导体层 在测量步骤结束时被识别为厚度的厚度的电感层。

公开(公告)号：US20150014822A1

公开(公告)日：2015-01-15

申请号：US14381537

申请日：2013-02-18

Applicant: Soitec

Inventor： Patrick Reynaud ,  Walter Schwarzenbach ,  Konstantin Bourdelle ,  Jean-Francois Gilbert

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L22/14 ,  G01R31/2601 ,  H01L22/20

Abstract: The invention concerns a method of testing a semiconductor on insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor on insulator type structures including carrying out the test on a sample structure from the batch.

Abstract translation: 本发明涉及一种测试半导体绝缘体类型结构的方法，包括支撑衬底，厚度小于50nm的电介质层和半导体层，该结构包括介电层和支撑衬底之间的接合界面或 半导体层或电介质层内部，其特征在于，其包括测量电介质层的电荷（QBD），并且从与层中和/或接合界面处的氢浓度相关的测量推导出信息。 本发明还涉及制造一批半导体绝缘体型结构的方法，包括对来自批料的样品结构进行测试。

公开(公告)号：US20250125140A1

公开(公告)日：2025-04-17

申请号：US18834122

申请日：2023-01-27

Applicant: Soitec

Inventor： Andrea Quintero-Colmenares ,  Frédéric Allibert ,  Alexis Drouin ,  Séverin Rouchier ,  Walter Schwarzenbach ,  Hugo Biard ,  Loïc Kabelaan ,  Oleg Kononchuk ,  Sidoine Odoul ,  Jérémy Roi

IPC: H01L21/02 ,  H01L21/324

Abstract: A method of manufacturing a polycrystalline silicon carbide wafer includes the following stages: heat treatment of a polycrystalline silicon carbide slab; thinning of the polycrystalline silicon carbide slab, the thinning comprising a correction, by withdrawal of material from the polycrystalline silicon carbide slab, of a deformation brought about by the heat treatment.

公开(公告)号：US20250072111A1

公开(公告)日：2025-02-27

申请号：US18937744

申请日：2024-11-05

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Manuel Sellier ,  Ludovic Ecarnot

IPC: H01L27/12 ,  H01L27/146

Abstract: The invention relates to a front-side imager comprising in succession: a semiconductor carrier substrate, a first electrically insulating separating layer, and a single-crystal semiconductor layer, called the active layer, comprising a matrix array of photodiodes, wherein the imager further comprises, between the carrier substrate and the first electrically insulating layer: a second electrically insulating separating layer, and a second semiconductor or electrically conductive layer, called the intermediate layer, arranged between the second separating layer and the first separating layer, the second separating layer being thicker than the first separating layer.

公开(公告)号：US12218201B2

公开(公告)日：2025-02-04

申请号：US17347417

申请日：2021-06-14

Applicant: Soitec ,  National University of Singapore

Inventor： Bich-Yen Nguyen ,  Christophe Maleville ,  Walter Schwarzenbach ,  Gong Xiao ,  Aaron Thean ,  Chen Sun ,  Haiwen Xu

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/265 ,  H01L21/84 ,  H01L27/10 ,  H01L27/12 ,  H01L29/161 ,  H01L29/78

Abstract: A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about −0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon-on-insulator device.

公开(公告)号：US12198975B2

公开(公告)日：2025-01-14

申请号：US17444230

申请日：2021-08-02

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot

IPC: H01L21/762 ,  H01L21/02 ,  H01L27/146 ,  H01L31/028

Abstract: A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.

公开(公告)号：US12148755B2

公开(公告)日：2024-11-19

申请号：US17254808

申请日：2019-06-21

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Manuel Sellier ,  Ludovic Ecarnot

IPC: H01L27/12 ,  H01L27/146

Abstract: The invention relates to a front-side imager comprising in succession: —a semiconductor carrier substrate, a first electrically insulating separating layer, and a single-crystal semiconductor layer, called the active layer, comprising a matrix array of photodiodes, wherein the imager further comprises between the carrier substrate and the first electrically insulating layer: —a second electrically insulating separating layer, and —a second semiconductor or electrically conductive layer, called the intermediate layer, arranged between the second separating layer and the first separating layer, the second separating layer being thicker than the first separating layer.