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公开(公告)号：US09024602B2
公开(公告)日：2015-05-05
申请号：US13848403
申请日：2013-03-21
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort , Thierry Soude
Abstract: The regulator with low dropout voltage comprises an error amplifier and an output stage comprising an output transistor and a buffer circuit comprising an input connected to the output node of the error amplifier, an output connected to the output transistor, a follower amplifier connected between the input and the output of the buffer circuit. The buffer circuit furthermore comprises a transistor active load connected to the output of the follower amplifier and a negative feedback amplifier arranged in common gate configuration and connected between the output of the follower amplifier and the gate of the transistor of the active load.
Abstract translation: 具有低压差电压的调节器包括误差放大器和输出级，输出级包括输出晶体管和缓冲电路，缓冲电路包括连接到误差放大器的输出节点的输入端，连接到输出晶体管的输出端，连接在输入端 和缓冲电路的输出。 缓冲电路还包括连接到从动放大器的输出的晶体管有源负载和以公共栅极配置布置并连接在从动放大器的输出端和有源负载晶体管的栅极之间的负反馈放大器。
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公开(公告)号：US20130257401A1
公开(公告)日：2013-10-03
申请号：US13848403
申请日：2013-03-21
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Jimmy Fort , Thierry Soude
IPC: G05F1/46
Abstract: The regulator with low dropout voltage comprises an error amplifier and an output stage comprising an output transistor and a buffer circuit comprising an input connected to the output node of the error amplifier, an output connected to the output transistor, a follower amplifier connected between the input and the output of the buffer circuit. The buffer circuit furthermore comprises a transistor active load connected to the output of the follower amplifier and a negative feedback amplifier arranged in common gate configuration and connected between the output of the follower amplifier and the gate of the transistor of the active load.
Abstract translation: 具有低压差电压的调节器包括误差放大器和输出级，输出级包括输出晶体管和缓冲电路，缓冲电路包括连接到误差放大器的输出节点的输入端，连接到输出晶体管的输出端，连接在输入端 和缓冲电路的输出。 缓冲电路还包括连接到从动放大器的输出的晶体管有源负载和以公共栅极配置布置并连接在从动放大器的输出端和有源负载晶体管的栅极之间的负反馈放大器。
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43.发明授权公开(公告)号：US11829178B2
公开(公告)日：2023-11-28
申请号：US17399617
申请日：2021-08-11
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Nicolas Demange , Nicolas Borrel , Jimmy Fort
CPC classification number: G05F3/262 , G06F21/755
Abstract: An embodiment electronic circuit power supply device is configured to: flow, through a first conductor connected to a node, a first current that is an image of a second current consumed by the electronic circuit; flow a third current through a second conductor connected to the node; regulate a potential of the node to a constant value by acting on the third current; flow a fourth constant current through a third conductor connected to the node; and consume a fifth current that is an image of the third current.
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公开(公告)号：US11137786B2
公开(公告)日：2021-10-05
申请号：US15931280
申请日：2020-05-13
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort , Maud Pierrel , Nicolas Borrel , Thierry Soude
IPC: G05F3/26
Abstract: An electronic device includes a starting circuit configured to compare a value representative of the power supply voltage with a threshold, wherein the circuit includes a generator of a current proportional to temperature.
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公开(公告)号：US20200371541A1
公开(公告)日：2020-11-26
申请号：US15931280
申请日：2020-05-13
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort , Maud Pierrel , Nicolas Borrel , Thierry Soude
IPC: G05F3/26
Abstract: An electronic device includes a starting circuit configured to compare a value representative of the power supply voltage with a threshold, wherein the circuit includes a generator of a current proportional to temperature.
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Patent Agency Ranking
公开(公告)号：US10685923B2
公开(公告)日：2020-06-16
申请号：US15916183
申请日：2018-03-08
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Alexandre Sarafianos , Jimmy Fort , Thierry Soude
Abstract: An electronic chip including a plurality of buried doped bars and a circuit for detecting an anomaly of an electric characteristic of the bars.
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公开(公告)号：US10673431B2
公开(公告)日：2020-06-02
申请号：US16161533
申请日：2018-10-16
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort , Nicolas Borrel , Francesco La Rosa
Abstract: A power supply voltage is monitored by a monitoring circuit including a variable current generator and a band gap voltage generator core receiving the variable current and including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the variable current generator generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.
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公开(公告)号：US20190086473A1
公开(公告)日：2019-03-21
申请号：US16059793
申请日：2018-08-09
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Nicolas Borrel , Jimmy Fort
IPC: G01R31/317 , G06F1/28 , G01R19/165
Abstract: A DC voltage glitch detection circuit, wherein a detection threshold is a function of this DC voltage.
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公开(公告)号：US09891639B2
公开(公告)日：2018-02-13
申请号：US14147814
申请日：2014-01-06
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort , Fabrice Marinet
CPC classification number: G05F1/462 , G06F1/26 , G06F1/3237 , G06F21/755 , Y02D10/128 , Y10T307/549
Abstract: The current signature of an electronic function is masked by controlling a current source that supplies power for the electronic function is controlled in a dynamically-varying manner. Excess current is detected and compared to a threshold. If the detected excess current meets the threshold, the operation of the electronic function is modified, for example by controlling a clock.
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公开(公告)号：US09804631B2
公开(公告)日：2017-10-31
申请号：US15243556
申请日：2016-08-22
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort , Thierry Soude
Abstract: A circuit includes a first PMOS transistor that includes a first PMOS source coupled to a first input node, a first PMOS gate, and a first PMOS drain. A second PMOS transistor includes a second PMOS source coupled to a second input node, a second PMOS gate, and a second PMOS drain coupled to the second PMOS gate. A first resistor coupled between the first PMOS source and a ground node. A first diode element coupled between the first resistor and the ground node and a second diode element coupled between the second PMOS source and the ground node. A third PMOS transistor includes a third PMOS gate, a third PMOS source coupled to a supply node, and a third PMOS drain coupled to the first input node. A fourth PMOS transistor includes a fourth PMOS gate coupled to the third PMOS gate, a fourth PMOS source coupled to the supply node, and a fourth PMOS drain coupled to the second input node.
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