公开(公告)号：US07902033B2

公开(公告)日：2011-03-08

申请号：US12029798

申请日：2008-02-12

申请人： Byron Lovell Williams ,  Maxwell Walthour Lippitt, III ,  Betty Mercer ,  Scott Montgomery ,  Binghua Hu

发明人： Byron Lovell Williams ,  Maxwell Walthour Lippitt, III ,  Betty Mercer ,  Scott Montgomery ,  Binghua Hu

IPC分类号： H01L21/20

CPC分类号： H01L28/91

摘要： An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.

摘要翻译： 实施例通常涉及形成电容器的方法。 该方法包括在集成电路的保护外涂层或后端电介质层内形成多个孔，并沉积多层金属，每层金属电连接到相关电极。 该方法还包括交替地在多层金属之间沉积多层电介质，并将多层金属的底层耦合到集成电路的顶层金属层中的接触节点。

公开(公告)号：US07772644B2

公开(公告)日：2010-08-10

申请号：US12509922

申请日：2009-07-27

申请人： Sameer Pendharkar ,  Binghua Hu

发明人： Sameer Pendharkar ,  Binghua Hu

IPC分类号： H01L29/78

CPC分类号： H01L29/66712 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7809 ,  H01L29/7816

摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.

摘要翻译： 一种LDMOS晶体管，其具有位于n型区域的外边界和p体区域的内边界之间的沟道区域。 LDMOS通道区域的宽度小于n +型区域的外边界与p体区域的内边界之间的距离的80％。 此外，制造LDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。 此外，VDMOS具有位于第一和第二p体区域的内边界和第一和第二p体区域的n型区域的外边界之间的第一和第二沟道区域。 VDMOS的第一和第二沟道区域的宽度小于第一和第二p体区域的内边界与第一和第二p体区域的n +型区域的外边界之间的距离的80％ 身体区域。 此外，制造VDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。

公开(公告)号：US07772075B2

公开(公告)日：2010-08-10

申请号：US12509935

申请日：2009-07-27

申请人： Sameer Pendharkar ,  Binghua Hu

发明人： Sameer Pendharkar ,  Binghua Hu

IPC分类号： H01L21/336

CPC分类号： H01L29/66712 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7809 ,  H01L29/7816

摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.

摘要翻译： 一种LDMOS晶体管，其具有位于n型区域的外边界和p体区域的内边界之间的沟道区域。 LDMOS通道区域的宽度小于n +型区域的外边界与p体区域的内边界之间的距离的80％。 此外，制造LDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。 此外，VDMOS具有位于第一和第二p体区域的内边界和第一和第二p体区域的n型区域的外边界之间的第一和第二沟道区域。 VDMOS的第一和第二沟道区域的宽度小于第一和第二p体区域的内边界与第一和第二p体区域的n +型区域的外边界之间的距离的80％ 身体区域。 此外，制造VDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。

公开(公告)号：US07732863B2

公开(公告)日：2010-06-08

申请号：US12120158

申请日：2008-05-13

申请人： Sameer Pendharkar ,  Binghua Hu

发明人： Sameer Pendharkar ,  Binghua Hu

IPC分类号： H01L29/78

CPC分类号： H01L29/66712 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7809 ,  H01L29/7816

摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.

摘要翻译： 一种LDMOS晶体管，其具有位于n型区域的外边界和p体区域的内边界之间的沟道区域。 LDMOS通道区域的宽度小于n +型区域的外边界与p体区域的内边界之间的距离的80％。 此外，制造LDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。 此外，VDMOS具有位于第一和第二p体区域的内边界和第一和第二p体区域的n型区域的外边界之间的第一和第二沟道区域。 VDMOS的第一和第二沟道区域的宽度小于第一和第二p体区域的内边界与第一和第二p体区域的n +型区域的外边界之间的距离的80％ 身体区域。 此外，制造VDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。

公开(公告)号：US20070105332A1

公开(公告)日：2007-05-10

申请号：US11470023

申请日：2006-09-05

申请人： Bill Wofford ,  Blake Pasker ,  Xinfen Chen ,  Binghua Hu

发明人： Bill Wofford ,  Blake Pasker ,  Xinfen Chen ,  Binghua Hu

IPC分类号： H01L29/94 ,  H01L21/20

CPC分类号： H01L28/40 ,  Y10S438/952

摘要： A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

摘要翻译： 公开了作为集成电路（IC）制造工艺的一部分形成的电容器（100）。 电容器（100）具有导电的顶部和底部电极（140,144）和非导电电容器电介质（142）。 在一个示例中，电介质（142）包括夹着抗反射材料层（118）的第一和第二薄介电层（112,114）。 薄层（112,114）提供电容器所需的电介质行为，而抗反射层（118）除其他之外通过减轻反射的驻波来促进减小的特征尺寸。

公开(公告)号：US07118959B2

公开(公告)日：2006-10-10

申请号：US11077074

申请日：2005-03-10

申请人： Bill Alan Wofford ,  Blake Ryan Pasker ,  Xinfen Chen ,  Binghua Hu

发明人： Bill Alan Wofford ,  Blake Ryan Pasker ,  Xinfen Chen ,  Binghua Hu

IPC分类号： H01L21/8242

CPC分类号： H01L28/40 ,  Y10S438/952

摘要： A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

摘要翻译： 公开了作为集成电路（IC）制造工艺的一部分形成的电容器（100）。 电容器（100）具有导电的顶部和底部电极（140,144）和非导电电容器电介质（142）。 在一个示例中，电介质（142）包括夹着抗反射材料层（118）的第一和第二薄介电层（112,114）。 薄层（112,114）提供电容器所需的电介质行为，而抗反射层（118）除其他之外通过减轻反射的驻波来促进减小的特征尺寸。

公开(公告)号：US08334190B2

公开(公告)日：2012-12-18

申请号：US12776057

申请日：2010-05-07

申请人： Eugene C. Davis ,  Binghua Hu ,  Sopa Chevacharoenkul ,  Prakash D. Dev

发明人： Eugene C. Davis ,  Binghua Hu ,  Sopa Chevacharoenkul ,  Prakash D. Dev

IPC分类号： H01L21/763 ,  H01L21/302

CPC分类号： C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L22/12 ,  H01L22/26

摘要： A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide layer on the SiNx layer, wherein trench access vias extend through the silicon oxide layer and SiNx layer to trenches formed into the semiconductor surface, and wherein a polysilicon layer fills the trench access vias, fills the trenches, and is on the silicon oxide layer. CMP polishes the multilayer film stack with a slurry including slurry particles including at least one of silica and ceria. The CMP provides a removal rate (RR) for the polysilicon layer > a RR for the silicon oxide layer > a RR for the SiNx layer. The CMP process is continued to remove the polysilicon layer, silicon oxide layer and a portion of the SiNx layer to stop on the SiNx layer. Optical endpointing during CMP can provide a predetermined remaining thickness range for the SiNx layer.

摘要翻译： 一种用于在其上具有多层膜堆叠的晶片上的三层或更多层膜堆叠的半导体表面上的氮化硅（SiNx）层和SiN x层上的氧化硅层的一步CMP工艺，其中沟槽通孔 延伸穿过硅氧化物层和SiNx层到形成半导体表面的沟槽，并且其中多晶硅层填充沟槽接通通孔，填充沟槽并且在氧化硅层上。 CMP用包括二氧化硅和二氧化铈中的至少一种的浆料颗粒的浆料抛光多层膜堆叠。 CMP提供多晶硅层的去除率（RR）>硅氧化物层的RR> SiNx层的RR。 继续进行CMP处理以去除SiN x层上的多晶硅层，氧化硅层和SiNx层的一部分。 CMP期间的光学终点可以为SiNx层提供预定的剩余厚度范围。

公开(公告)号：US08148228B2

公开(公告)日：2012-04-03

申请号：US11696829

申请日：2007-04-05

申请人： Sameer Pendharkar ,  Binghua Hu ,  Xinfen Celia Chen

发明人： Sameer Pendharkar ,  Binghua Hu ,  Xinfen Celia Chen

IPC分类号： H01L21/8228

CPC分类号： H01L29/7322 ,  H01L23/544 ,  H01L29/41708 ,  H01L29/66272 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an oxide-converted first thickness of the implanted sub-regions is greater than an oxide-converted second thickness of the non-implanted areas. The method further comprises removing the oxide layer to form a topography feature on the well region. The topography feature comprises a surface pattern of higher and lower portions. The higher portions correspond to locations of the non-implanted areas and the lower portions correspond to the implanted sub-regions.

摘要翻译： 一种用于制造半导体器件的方法，包括在衬底的阱区中注入第一掺杂剂类型以形成由所述阱区的非植入区域分离的注入的子区。 该方法还包括在阱区上形成氧化物层，使得注入的子区域的氧化物转化的第一厚度大于非植入区域的氧化物转化的第二厚度。 该方法还包括去除氧化物层以在阱区上形成形貌特征。 地形特征包括较高和较低部分的表面图案。 更高的部分对应于非植入区域的位置，并且下部对应于植入的子区域。

公开(公告)号：US08124482B2

公开(公告)日：2012-02-28

申请号：US13006589

申请日：2011-01-14

申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

IPC分类号： H01L21/336

CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

公开(公告)号：US07808071B2

公开(公告)日：2010-10-05

申请号：US12166395

申请日：2008-07-02

申请人： Binghua Hu ,  Mindricelu P. Eugen ,  Damien T. Gilmore ,  Bill A. Wofford

发明人： Binghua Hu ,  Mindricelu P. Eugen ,  Damien T. Gilmore ,  Bill A. Wofford

IPC分类号： H01L21/02

CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823462 ,  H01L29/6659 ,  H01L29/7833

摘要： One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.

摘要翻译： 半导体器件的一个方面包括位于半导体衬底中并具有位于其间的隔离区的有源区。 有源区域具有邻近隔离区域的角。 氧化物层位于有源区域和角部之上，角部还可以包括有源区域的边缘，并且在活性区域上的角部上的氧化物层的厚度与氧化物层的厚度之比约为约 0.6：1至约0.8：1。 栅极位于有源区和氧化物层之上。