公开(公告)号：US12100442B2

公开(公告)日：2024-09-24

申请号：US17682100

申请日：2022-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Daeseok Byeon ,  Hyunsurk Ryu

IPC: G11C11/4093 ,  G06N3/063 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4094 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C11/4093 ,  G06N3/063 ,  G11C5/06 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4094 ,  G11C16/0483 ,  G11C16/08

Abstract: Flash memory device includes: first pads to be bonded to external semiconductor chip, to receive at least one of command, address and control signals; second pads to be bonded to external semiconductor chip; memory cell array including memory cells; a row decoder block connected to memory cell array through word lines, to select one of word lines based on address provided to row decoder block; a buffer block to store command and address and provide address to row decoder block; a page buffer block connected to memory cell array through bit lines, connected to second pads through data lines without passing through buffer block, and configured to exchange data signals with external semiconductor chip through data lines and second pads; and a control logic block configured to receive command from buffer block, to receive control signals from external semiconductor chip, and to control row decoder block and page buffer block.

公开(公告)号：US11823888B2

公开(公告)日：2023-11-21

申请号：US17025300

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-Yeol Lee ,  Chanho Kim

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a peripheral circuit layer, a first memory layer provided on the peripheral circuit layer, an inter-metal layer provided on the first memory layer, and a second memory layer provided on the inter-metal layer. The peripheral circuit layer includes a first substrate and a peripheral circuit provided on the first substrate. The first memory layer includes a first memory structure electrically connected to the peripheral circuit through metal bonding pads. The inter-metal layer includes intermediate pads electrically connected to the peripheral circuit through metal bonding pads. The second memory layer includes a second memory structure electrically connected with the intermediate pads and a second substrate provided on the second memory structure. The peripheral circuit, the first memory structure, and the second structure are provided between the first substrate and the second substrate.

公开(公告)号：US11621256B2

公开(公告)日：2023-04-04

申请号：US17393934

申请日：2021-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Dongku Kang ,  Daeseok Byeon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/18 ,  H01L23/00

Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

公开(公告)号：US11411018B2

公开(公告)日：2022-08-09

申请号：US16923636

申请日：2020-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Daeseok Byeon ,  Dongku Kang

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/535 ,  H01L27/11565

Abstract: An integrated circuit (IC) device includes a peripheral circuit structure, a memory stack including a plurality of gate lines overlapping the peripheral circuit structure in a vertical direction on the peripheral circuit structure, an upper substrate between the peripheral circuit structure and the memory stack, the upper substrate including a through hole positioned below a memory cell region of the memory stack, a word line cut region extending lengthwise in a first lateral direction across the memory stack and the through hole, and a common source line located in the word line cut region, the common source line including a first portion extending lengthwise in the first lateral direction on the upper substrate and a second portion integrally connected to the first portion, the second portion penetrating the upper substrate through the through hole from an upper portion of the upper substrate and extending into the peripheral circuit structure.

公开(公告)号：US11355194B2

公开(公告)日：2022-06-07

申请号：US16942299

申请日：2020-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Pansuk Kwak

IPC: G11C16/08 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

Abstract: A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.

公开(公告)号：US11348848B2

公开(公告)日：2022-05-31

申请号：US17006186

申请日：2020-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyo Kim ,  Chanho Kim ,  Daeseok Byeon

IPC: H01L27/11573 ,  H01L21/66 ,  H01L23/00

Abstract: A nonvolatile memory device includes a memory cell region including first pads and a peripheral circuit region including second pads. The regions comprises switches that are electrically connected with the pads, respectively, a test signal generator that generates test signals and to transmit the test signals to the switches, internal circuits that receive first signals through the pads and the switches, to perform operations based on the first signals, and to output second signals through the switches and the pads based on a result of the operations, and a switch controller that controls the switches so that the pads communicate with the test signal generator during a test operation and that the pads communicate with the internal circuits after a completion of the test operation. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

公开(公告)号：US11264084B2

公开(公告)日：2022-03-01

申请号：US16871815

申请日：2020-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Daeseok Byeon ,  Hyunsurk Ryu

IPC: G11C11/4093 ,  G11C16/08 ,  G11C16/04 ,  G11C11/4094 ,  G11C5/06 ,  G11C11/408

Abstract: A flash memory device includes: first pads; second pads; third pads; a memory cell array; a row decoder block; a buffer block that stores a command and an address received from an external semiconductor chip through the first pads and provides the address to the row decoder block; a page buffer block that is connected to the memory cell array through bit lines, is connected to the third pads through data lines, and exchanges data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block that receives the command from the buffer block, receives control signals from the external semiconductor chip through the second pads, and controls the row decoder block and the page buffer block based on the received command and the received control signals.

公开(公告)号：US11264082B2

公开(公告)日：2022-03-01

申请号：US17024267

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/02 ,  G11C5/06 ,  G11C11/408

Abstract: A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight, wherein the plurality of first memory cells and the plurality of second memory cells are included in a first chip having a first metal pad, the first peripheral circuit and the second peripheral circuit are included in a second chip having a second metal pad, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US11233043B2

公开(公告)日：2022-01-25

申请号：US17002149

申请日：2020-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Joo-Yong Park ,  Daeseok Byeon

IPC: H01L25/18 ,  H01L23/00

Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.

公开(公告)号：US11211391B2

公开(公告)日：2021-12-28

申请号：US16814491

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa Yun ,  Pansuk Kwak ,  Chanho Kim ,  Dongku Kang

IPC: G11C16/04 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C5/02

Abstract: A memory device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder; a cell array region including wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating through the wordlines; and a cell contact region including cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction. Each of the first and second cell contact regions includes first pads having different lengths to each other in the first direction and second pads different from the first pads, and the cell contacts are connected to the wordlines in the first pads. The number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region.