公开(公告)号：US11658107B2

公开(公告)日：2023-05-23

申请号：US17807894

申请日：2022-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Hyunkyu Kim ,  Jongbo Shim ,  Eunhee Jung ,  Kyoungsei Choi

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/45 ,  H01L25/0657

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US11581263B2

公开(公告)日：2023-02-14

申请号：US17024852

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jungsoo Byun ,  Jongbo Shim ,  Doohwan Lee ,  Kyoungsei Choi ,  Junggon Choi ,  Sungeun Pyo

IPC: H01L23/495 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.

公开(公告)号：US11367679B2

公开(公告)日：2022-06-21

申请号：US17017638

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Hyunkyu Kim ,  Jongbo Shim ,  Eunhee Jung ,  Kyoungsei Choi

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US10923428B2

公开(公告)日：2021-02-16

申请号：US16432551

申请日：2019-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Kilsoo Kim ,  Jongbo Shim ,  Jangwoo Lee ,  Eunhee Jung

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a substrate, a semiconductor chip mounted on the substrate, an interposer chip on the semiconductor chip and including a redistribution pattern, a first pad on the interposer chip, a second pad on the interposer chip and spaced apart from the first pad, and a bonding wire electrically connected to the second pad and the first substrate. The second pad is electrically connected through the redistribution pattern to the first pad. The footprint of the interposer chip is greater than the footprint of the first semiconductor chip.

公开(公告)号：US20190214423A1

公开(公告)日：2019-07-11

申请号：US16058451

申请日：2018-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Chajea Jo ,  Hyoeun Kim ,  Jongbo Shim ,  Sang-uk Han

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14634 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0557 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/16104 ,  H01L2224/16145

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.