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52 条记录 (耗时 0.026 秒)

    Power circuit package
    41.
    发明授权
    Power circuit package 失效
    电源电路封装

    公开(公告)号：US5508559A

    公开(公告)日：1996-04-16

    申请号：US233100

    申请日：1994-04-25

    申请人： Samuel J. Anderson ,  Guillermo L. Romero

    发明人： Samuel J. Anderson ,  Guillermo L. Romero

    IPC分类号： H01L23/02 ,  H01L23/373 ,  H01L23/473 ,  H01L25/07 ,  H03B1/00 ,  H03B7/06 ,  H01L23/06

    CPC分类号： H01L25/072 ,  H01L23/3731 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B2200/0034 ,  H03B2200/004 ,  H03B2201/0208 ,  H03B7/06 ,  Y10T29/4913

    摘要： A method for forming a power circuit package (45) having a porous base structure (20) electrically isolated from a first porous die mount (21) and a second porous die mount (22) by a dielectric material (29). The porous base structure (20) is bonded to a second surface of the the dielectric material (29) whereas the first porous die mount (21), and the second porous die mount (22) are bonded to a first surface of the dielectric material (29). Simultaneous with the bonding step, the porous base structure (20), the first porous die mount (21), and the second porous die mount (22) are impregnated with a conductive material. Semiconductor die (32, 33, 34, and 35) are bonded to the impregnated die mounts. The semiconductor die (32, 33, 34, and 35) are then encapsulated by a molding compound.

    摘要翻译： 一种用于形成具有通过介电材料（29）与第一多孔管芯安装件（21）电隔离的多孔基底结构（20）和第二多孔管芯安装件（22）的电源电路封装（45）的方法。 所述多孔基底结构（20）与所述电介质材料（29）的第二表面接合，而所述第一多孔模座（21）和所述第二多孔模座（22）与所述电介质材料 （29）。 与接合步骤同时，多孔基底结构（20），第一多孔模座（21）和第二多孔模座（22）浸渍有导电材料。 半导体管芯（32,33,34和35）与浸渍的模具安装座结合。 然后，半导体管芯（32,33,34和35）被模塑料包封。

    Method of forming an insulated gate semiconductor device
    42.
    发明授权
    Method of forming an insulated gate semiconductor device 失效
    形成绝缘栅半导体器件的方法

    公开(公告)号：US5397716A

    公开(公告)日：1995-03-14

    申请号：US55581

    申请日：1993-05-03

    申请人： Samuel J. Anderson

    发明人： Samuel J. Anderson

    IPC分类号： H01L29/739 ,  H01L21/265

    CPC分类号： H01L29/7395

    摘要： A method of forming an insulated gate semiconductor device (10). A field effect transistor and a bipolar transistor are formed in a portion of a monocrystalline semiconductor substrate (11) that is bounded by a first major surface (12). A control electrode (19) is isolated from the first major surface by a dielectric layer (18). A first current conducting electrode (23) contacts a portion of the first major surface (12). A second current conducting electrode (24) contacts another portion of the monocrystalline semiconductor substrate (11) and is capable of injecting minority carriers into the monocrystalline semiconductor substrate (11). In one embodiment, the second current conducting electrode contacts a second major surface (13) of the monocrystalline semiconductor substrate (11).

    摘要翻译： 一种形成绝缘栅半导体器件（10）的方法。 在由第一主表面（12）限定的单晶半导体衬底（11）的一部分中形成场效应晶体管和双极晶体管。 控制电极（19）通过电介质层（18）与第一主表面隔离。 第一电流导电电极（23）接触第一主表面（12）的一部分。 第二电流导电电极（24）接触单晶半导体衬底（11）的另一部分，并且能够将少数载流子注入到单晶半导体衬底（11）中。 在一个实施例中，第二电流传导电极接触单晶半导体衬底（11）的第二主表面（13）。

    Plastic encapsulated microelectronic device and method
    43.
    发明授权
    Plastic encapsulated microelectronic device and method 失效
    塑料封装微电子器件及方法

    公开(公告)号：US5378928A

    公开(公告)日：1995-01-03

    申请号：US52962

    申请日：1993-04-27

    申请人： Samuel J. Anderson ,  John Baird ,  Martin A. Kalfus

    发明人： Samuel J. Anderson ,  John Baird ,  Martin A. Kalfus

    IPC分类号： H01L23/31 ,  H01L23/16 ,  H01L23/28

    CPC分类号： H01L23/3121 ,  H01L2924/0002 ,  Y10T29/49144 ,  Y10T29/49146

    摘要： An encapsulated microelectronic device (100) including a base (101) and a semiconductor device (305) having a top and a bottom. The bottom is attached to the base (101). The semiconductor device (105) has a thickness in the range from one-fourth to three-fourths of a millimeter and has a bottom metallization consisting of aluminum (407)/chromium (405)/nickel (403)/gold (401). The semiconductor device (305) has a contact (115) attached to the top. The encapsulated microelectronic device (100) has a molded top (120) surrounding the semiconductor device (305). The molded top (120) is made from low stress molding material.

    摘要翻译： 一种封装的微电子器件（100），包括具有顶部和底部的基底（101）和半导体器件（305）。 底部附接到基座（101）。 半导体器件（105）的厚度在一毫米的四分之一至四分之四的范围内，并且具有由铝（407）/铬（405）/镍（403）/金（401）组成的底部金属化。 半导体器件（305）具有附接到顶部的触点（115）。 封装的微电子器件（100）具有围绕半导体器件（305）的模制顶部（120）。 模制顶部（120）由低应力模制材料制成。

    Mounting bracket for venetian blind assembly
    44.
    发明授权
    Mounting bracket for venetian blind assembly 失效
    用于百叶窗组装的安装支架

    公开(公告)号：US4224974A

    公开(公告)日：1980-09-30

    申请号：US969093

    申请日：1978-12-13

    申请人： James M. Anderson ,  Samuel J. Anderson

    发明人： James M. Anderson ,  Samuel J. Anderson

    IPC分类号： E06B9/323 ,  E06B9/38

    CPC分类号： E06B9/323 ,  Y10S160/902

    摘要： A bracket for mounting the head rail of a venetian blind to a support surface of a window opening. The head rail is in the form of channel member of U-shaped cross section comprising a base member pivotally mounted to a support surface, a pair of flexible, resilient legs depending from the base member having tangs at their terminal ends engageable with locking beads running the length of the head rail channel and rotatable to a position wherein the tangs release the channel member.

    摘要翻译： 用于将百叶窗的头轨安装到窗口的支撑表面的支架。 头轨是U形横截面的通道构件的形式，其包括枢转地安装到支撑表面的基部构件，一对柔性弹性腿，其从基部构件悬垂，在其末端具有柄脚，其可与锁定珠运动 头轨道的长度并且可旋转到其中柄脚释放通道构件的位置。

    Venetian blind assembly and mounting means therefor
    45.
    发明授权
    Venetian blind assembly and mounting means therefor 失效
    百叶窗组装和安装方式

    公开(公告)号：US4177853A

    公开(公告)日：1979-12-11

    申请号：US798649

    申请日：1977-05-19

    申请人： Samuel J. Anderson ,  James M. Anderson

    发明人： Samuel J. Anderson ,  James M. Anderson

    IPC分类号： E06B9/323 ,  E06B9/388 ,  E06B9/30

    CPC分类号： E06B9/388 ,  E06B9/323

    摘要： A mounting bracket which is simple, economic to manufacture and easy to install for the detachable mounting the head rail of a venetian blind assembly in a window opening or the like. In one form the bracket is of box-like configuration having panels with means for securing it to the side, top or front support surface of the window frame, a hinged front panel permitting pivoting from an open position to receive the ends of the head rail and locking means for latching the front panel in a closed position with the head rail in place. In another form, the bracket has flexible legs with tangs to engage with longitudinal ribs in the head rail and is pivotally mounted to release from the head rail when desired. Other features include a bumper insert for the head rail to resist transverse displacement when raising and lowering the blind and a novel control rod and ladder string arrangement facilitating complete closing of all the slats.

    摘要翻译： 一种安装支架，其简单，经济地制造并且易于安装，用于将窗帘组件的头轨可拆卸地安装在窗户开口等中。 在一种形式中，支架具有盒状构造，其具有用于将其固定到窗框的侧面，顶部或前支撑表面的装置的面板，铰接的前面板允许从打开位置枢转以接收头轨的端部 以及锁定装置，用于将头板固定就位，将前面板锁定在关闭位置。 在另一种形式中，支架具有柔性腿部，脚部具有与头部导轨中的纵向肋接合，并且当需要时枢转地安装以从头部轨道释放。 其他特征包括用于头部导轨的保险杠插入件，以在升高和降低盲板时抵抗横向位移，以及一种新颖的控制杆和梯形排列装置，便于所有板条的完全关闭。

    Fast block device, system and methodology
    46.
    发明授权
    Fast block device, system and methodology 有权

    公开(公告)号：US10817185B1

    公开(公告)日：2020-10-27

    申请号：US15396904

    申请日：2017-01-03

    申请人： Douglas Dumitru ,  Samuel J. Anderson

    发明人： Douglas Dumitru ,  Samuel J. Anderson

    IPC分类号： G06F3/06 ,  G06F12/00

    摘要： A device, memory, method and system directed to fast data storage on a block storage device that reduces operational wear on the device. New data is written to an empty write block with a number of write blocks being reused. A location of the new data is tracked. Metadata associated with the new data is written. A lookup table may be updated based in part on the metadata. The new data may be read based the lookup table configured to map a logical address to a physical address.

    Semiconductor device and method of forming low voltage MOSFET for portable electronic devices and data processing centers
    49.
    发明授权
    Semiconductor device and method of forming low voltage MOSFET for portable electronic devices and data processing centers 有权
    用于形成用于便携式电子设备和数据处理中心的低压MOSFET的半导体器件和方法

    公开(公告)号：US08138558B2

    公开(公告)日：2012-03-20

    申请号：US12859943

    申请日：2010-08-20

    申请人： Patrick M. Shea ,  Samuel J. Anderson

    发明人： Patrick M. Shea ,  Samuel J. Anderson

    IPC分类号： H01L27/088

    CPC分类号： H01L29/7833 ,  H01L21/743 ,  H02M3/33523

    摘要： A semiconductor device has a well region formed within a substrate. A gate structure is formed over a surface of the substrate. A source region is formed within the substrate adjacent to the gate structure. A drain region is formed within the substrate adjacent to the gate structure. A first clamping region and second clamping region below the source region and drain region. A trench is formed through the source region. The trench allows the width of the source region to be reduced to 0.94 to 1.19 micrometers. A plug is formed through the trench. A source tie is formed through the trench over the plug. An interconnect structure is formed over the source region, drain region, and gate structure. The semiconductor device can be used in a power supply to provide a low voltage to electronic equipment such as a portable electronic device and data processing center.

    摘要翻译： 半导体器件具有在衬底内形成的阱区。 在衬底的表面上形成栅极结构。 源极区域形成在与栅极结构相邻的衬底内。 漏极区域形成在与栅极结构相邻的衬底内。 源极区域和漏极区域之下的第一钳位区域和第二钳位区域。 通过源极区形成沟槽。 沟槽允许源极区域的宽度减小到0.94至1.19微米。 通过沟槽形成插头。 通过插塞上的沟槽形成源极连接。 在源极区，漏极区和栅极结构上形成互连结构。 该半导体器件可用于电源中，以向便携式电子设备和数据处理中心等电子设备提供低电压。