公开(公告)号：US11189335B2

公开(公告)日：2021-11-30

申请号：US16683209

申请日：2019-11-13

Applicant: SanDisk Technologies LLC

Inventor： Masatoshi Nishikawa ,  Hardwell Chibvongodze ,  Ken Oowada

IPC: G11C11/408 ,  G11C7/14 ,  G11C11/4094 ,  H01L27/06 ,  G11C11/4074 ,  G11C11/56 ,  G11C11/4091

Abstract: A three-dimensional (3D) memory is provided, including a memory array chip and a complementary metal-oxide semiconductor (CMOS) chip disposed on the memory array chip. The memory chip provides double write/read throughput and includes a lower region with a lower array of memory cells, lower word lines, and a lower bit line, while an upper region includes an upper array of memory cells, upper word lines, and an upper bit line. A source line is disposed between the lower and upper regions and is connected to both the lower array of memory cells and the upper array of memory cells.

公开(公告)号：US20210233589A1

公开(公告)日：2021-07-29

申请号：US17227820

申请日：2021-04-12

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Aaron Lee ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.

公开(公告)号：US10971231B1

公开(公告)日：2021-04-06

申请号：US16912720

申请日：2020-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rajdeep Gautam ,  Hardwell Chibvongodze ,  Ken Oowada

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/28

Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.

公开(公告)号：US10756106B2

公开(公告)日：2020-08-25

申请号：US16202713

申请日：2018-11-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Michiaki Sano ,  Ken Oowada ,  Zhixin Cui

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/8234 ,  H01L27/11524 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.

公开(公告)号：US10741579B2

公开(公告)日：2020-08-11

申请号：US16215912

申请日：2018-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Masatoshi Nishikawa ,  Ken Oowada

IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L23/528 ,  H01L21/311 ,  H01L21/762 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/36 ,  H01L21/306

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.