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    METHOD FOR OBTAINING SMOOTH, CONTINUOUS SILVER FILM
    41.
    发明申请
    METHOD FOR OBTAINING SMOOTH, CONTINUOUS SILVER FILM 有权
    用于获得平滑，连续镀膜的方法

    公开(公告)号：US20120252183A1

    公开(公告)日：2012-10-04

    申请号：US13461725

    申请日：2012-05-01

    申请人： Scott Brad Herner

    发明人： Scott Brad Herner

    IPC分类号： H01L21/02

    CPC分类号： H01L45/1675 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1616

    摘要： A method for forming a semiconductor device including a resistive memory cell includes providing a substrate having an upper surface. A first conductive layer is formed over the upper surface of the substrate. An amorphous silicon layer is formed over the first conductive layer. A surface of the amorphous silicon layer is cleaned to remove native oxide formed on the surface of the amorphous silicon layer. A silver layer is deposited over the amorphous silicon layer after removing the native oxide by performing the cleaning step. The resistive memory cell includes the first conductive layer, the amorphous silicon layer, and the second conductive layer. The surface of the amorphous silicon layer is cleaned to prevent silver agglomeration on the native oxide.

    摘要翻译： 一种形成包括电阻式存储单元的半导体器件的方法包括提供具有上表面的衬底。 在衬底的上表面上形成第一导电层。 在第一导电层上形成非晶硅层。 清洁非晶硅层的表面以去除在非晶硅层的表面上形成的自然氧化物。 通过执行清洁步骤去除天然氧化物之后，在非晶硅层上沉积银层。 电阻式存储单元包括第一导电层，非晶硅层和第二导电层。 清洁非晶硅层的表面以防止在自然氧化物上的银团聚。

    IMPROVED ON/OFF RATIO FOR NON-VOLATILE MEMORY DEVICE AND METHOD
    42.
    发明申请
    IMPROVED ON/OFF RATIO FOR NON-VOLATILE MEMORY DEVICE AND METHOD 有权
    用于非易失性存储器件的改进的ON / OFF比率和方法

    公开(公告)号：US20120012806A1

    公开(公告)日：2012-01-19

    申请号：US12835699

    申请日：2010-07-13

    申请人： Scott Brad Herner

    发明人： Scott Brad Herner

    IPC分类号： H01L45/00 ,  H01L21/02

    CPC分类号： H01L45/1273 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

    摘要： This application describes a method of forming a switching device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms a first opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying at lease the top surface region of the switching element such that the conductive material is in direct contact with the switching element. The side wall spacer reduces a contact area for the switching element and the conductive material and thus a reduced active device area for the switching device. In a specific embodiment, the reduced area provides for an increase in device ON/OFF current ratio.

    摘要翻译： 该应用描述了形成开关器件的方法。 该方法包括形成覆盖在衬底的表面区域上的第一电介质材料。 底部布线材料形成在第一介电材料上方，并且覆盖在底部布线材料上的开关材料沉积。 对底部布线材料和开关材料进行第一图案化和蚀刻工艺以形成具有顶表面区域和侧面区域的第一结构。 第一结构至少包括底部布线结构和具有包括开关元件的暴露区域的顶表面区域的开关元件。 至少形成包括开关元件的暴露区域的第一结构的第二电介质材料。 该方法在第二电介质层的一部分中形成第一开口区域以暴露开关元件的顶表面区域的一部分。 电介质侧壁结构形成在第一开口区域的侧面上。 包括导电材料的顶部布线材料形成为覆盖开关元件的顶表面区域，使得导电材料与开关元件直接接触。 侧壁间隔物减少了开关元件和导电材料的接触面积，并因此降低了用于开关器件的有源器件面积。 在具体实施例中，减小的面积提供了器件ON / OFF电流比的增加。

    p+ polysilicon material on aluminum for non-volatile memory device and method
    43.
    发明授权
    p+ polysilicon material on aluminum for non-volatile memory device and method 有权
    p +多晶硅材料在铝上用于非易失性存储器件和方法

    公开(公告)号：US08088688B1

    公开(公告)日：2012-01-03

    申请号：US12940920

    申请日：2010-11-05

    申请人： Scott Brad Herner

    发明人： Scott Brad Herner

    IPC分类号： H01L21/44 ,  H01L29/02 ,  H01L29/40

    CPC分类号： H01L45/085 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1683

    摘要： A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material comprising at least an aluminum material is formed overlying the first dielectric material. The method forms a silicon material overlying the aluminum material and forms an intermix region consuming a portion of the silicon material and a portion of the aluminum material. The method includes an annealing process to cause formation of a first alloy material from the intermix region and a polycrystalline silicon material having a p+ impurity characteristic overlying the first alloy material. A first wiring structure is formed from at least a portion of the first wiring material. A resistive switching element comprising an amorphous silicon material is formed overlying the polycrystalline silicon material having the p+ impurity characteristic. A second wiring structure comprising at least a metal material is formed overlying the resistive switching element.

    摘要翻译： 一种形成非易失性存储器件的方法。 该方法包括提供具有表面区域并形成覆盖在表面区域上的第一电介质材料的衬底。 至少包含铝材料的第一布线材料形成在第一介电材料上。 该方法形成覆盖铝材料的硅材料，并形成消耗硅材料的一部分和铝材料的一部分的混合区域。 该方法包括从混合区域形成第一合金材料的退火工艺和具有覆盖在第一合金材料上的p +杂质特性的多晶硅材料。 第一布线结构由第一布线材料的至少一部分形成。 包含非晶硅材料的电阻式开关元件形成在具有p +杂质特性的多晶硅材料上。 包括至少金属材料的第二布线结构形成在电阻式开关元件上。

    Method for making a P-I-N diode crystallized adjacent to a silicide in series with a dielectric antifuse
    44.
    发明授权
    Method for making a P-I-N diode crystallized adjacent to a silicide in series with a dielectric antifuse 有权
    使与绝缘反熔丝串联的硅化物附近结晶的P-I-N二极管的方法

    公开(公告)号：US08003477B2

    公开(公告)日：2011-08-23

    申请号：US12698253

    申请日：2010-02-02

    申请人： Scott Brad Herner

    发明人： Scott Brad Herner

    IPC分类号： H01L21/331

    CPC分类号： H01L23/5252 ,  G11C13/0069 ,  G11C17/16 ,  G11C2013/009 ,  G11C2213/33 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A method is described for monolithically forming a first memory level above a substrate, the method including: (a) forming a plurality of first substantially parallel, substantially coplanar conductors above the substrate, the first conductors extending in a first direction; (b) forming a plurality of vertically oriented contiguous p-i-n diodes above the first conductors, the contiguous p-in diode comprising semiconductor material crystallized in contact with a silicide, silicide-germanide, or germanide layer; (c) forming a plurality of second substantially parallel, substantially coplanar conductors, the second conductors above the contiguous p-i-n diodes, the second conductors extending in a second direction different from the first direction, each contiguous p-i-n diode vertically disposed between one of the first conductors and one of the second conductors; (d) and forming a plurality of dielectric rupture antifuses, each dielectric rupture antifuse disposed between one of the contiguous p-i-n diodes and one of the first conductors or between one of the contiguous p-i-n diodes and one of the second conductors, wherein the dielectric rupture antifuses comprise dielectric material, the dielectric material having a dielectric constant greater than about 8. Other aspects are provided.

    摘要翻译： 描述了一种用于在衬底上单层形成第一存储器电平的方法，所述方法包括：（a）在衬底上方形成多个第一基本平行的基本上共面的导体，所述第一导体沿第一方向延伸; （b）在所述第一导体上方形成多个垂直取向的连续p-i-n二极管，所述连续p-in二极管包括与硅化物，硅化物 - 锗化物或锗化锗层接触结晶的半导体材料; （c）形成多个第二基本上平行的基本上共面的导体，所述第二导体位于所述相邻引脚二极管之上，所述第二导体沿与第一方向不同的第二方向延伸，每个相邻的引脚二极管垂直地设置在所述第一导体 和第二导体之一; （d）并且形成多个介电破裂反熔丝，每个介质断裂反熔丝设置在一个连续的pin二极管和一个第一导体之间，或者在一个连续的pin二极管和一个第二导体之间，其中介质断裂反熔丝 包括电介质材料，介电材料的介电常数大于约8.其它方面。

    Reduced fluorine contamination for tungsten CVD
    45.
    发明授权
    Reduced fluorine contamination for tungsten CVD 失效
    降低钨CVD的氟污染

    公开(公告)号：US06429126B1

    公开(公告)日：2002-08-06

    申请号：US09538379

    申请日：2000-03-29

    申请人： Scott Brad Herner ,  Sandeep A. Desai

    发明人： Scott Brad Herner ,  Sandeep A. Desai

    IPC分类号： H01L2144

    CPC分类号： C23C16/14 ,  C23C16/0281 ,  H01L21/28556 ,  H01L21/76877

    摘要： A chemical vapor deposition process for depositing a tungsten film on a substrate disposed in a substrate processing. The method includes depositing nucleation and bulk deposition tungsten layers. The nucleation layer is deposited by flowing a first process gas comprising tungsten hexafluoride, silane, molecular hydrogen and argon into said substrate processing chamber, where the flow ratio of molecular hydrogen to argon is at least 1.5:1 and the partial pressure of tungsten hexafluoride is less than or equal to 0.5 Torr. The bulk deposition layer is then deposited over the nucleation layer by flowing a second process gas comprising tungsten hexafluoride and a reduction agent into the substrate processing chamber.

    摘要翻译： 一种用于在设置在基板处理中的基板上沉积钨膜的化学气相沉积工艺。 该方法包括沉积成核和体积沉积钨层。 通过将包含六氟化钨，硅烷，分子氢和氩的第一工艺气体流入所述衬底处理室来沉积成核层，其中分子氢与氩的流量比至少为1.5:1，六氟化钨的分压为 小于或等于0.5托。 然后通过使包含六氟化钨和还原剂的第二工艺气体流入基板处理室，将沉积层沉积在成核层上。

    Package-less LED assembly and method
    48.
    发明授权
    Package-less LED assembly and method 有权

    公开(公告)号：US10026864B2

    公开(公告)日：2018-07-17

    申请号：US15043540

    申请日：2016-02-13

    申请人： Scott Brad Herner

    发明人： Scott Brad Herner

    IPC分类号： H01L33/00

    摘要： This application describes an assembly suitable for emitting light, and methods of forming the same. The assembly includes a single crystal substrate with first and second surfaces, a plurality of LEDs in immediate contact with the first surface of the substrate. The LEDs are substantially crystal lattice matched with the substrate. The plurality of LEDs includes three or more LEDs that are not in electrical contact with any other LED, and there is a gap between each LED of the plurality and its nearest neighbor LED. The assembly includes phosphor-containing encapsulant layers overlying at least a portion of the LEDs.