公开(公告)号：US07960229B2

公开(公告)日：2011-06-14

申请号：US12100598

申请日：2008-04-10

Applicant: Frank Bin Yang ,  Rohit Pal ,  Scott Luning

Inventor： Frank Bin Yang ,  Rohit Pal ,  Scott Luning

IPC: H01L21/336

CPC classification number: H01L29/66628 ,  H01L29/66772 ,  H01L29/78618

Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

Abstract translation: 提供了具有减小的栅极高度的金属氧化物半导体晶体管器件。 器件的一个实施例包括具有半导体材料层的衬底，覆盖半导体材料层的栅极结构以及形成在与栅极结构相邻的半导体材料中的源极/漏极凹槽，使得剩余的半导体材料位于 源极/漏极凹槽。 器件还包括在剩余半导体材料中形成的浅源极/漏极注入区域，以及在源极/漏极凹槽中外延生长的原位掺杂的半导体材料。

公开(公告)号：US07829401B2

公开(公告)日：2010-11-09

申请号：US12121387

申请日：2008-05-15

Applicant: Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

Inventor： Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

Abstract translation: 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

公开(公告)号：US07504301B2

公开(公告)日：2009-03-17

申请号：US11536126

申请日：2006-09-28

Applicant: Andrew M. Waite ,  Scott Luning

Inventor： Andrew M. Waite ,  Scott Luning

IPC: H01L21/00

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

Abstract translation: 提供了一种应力场效应晶体管及其制造方法。 场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。 栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。 具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。 具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

公开(公告)号：US20080268609A1

公开(公告)日：2008-10-30

申请号：US12131214

申请日：2008-06-02

Applicant: Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

Inventor： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

IPC: H01L21/76

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/84

Abstract: Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.

Abstract translation: 公开了用于提供用于混合表面取向结构的堆垛层错缺陷外延生长的硅的方法。 在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫 并且在开口中外延生长硅。 由于底切产生的负斜率，硅片堆积层错误大大减少。

公开(公告)号：US07183169B1

公开(公告)日：2007-02-27

申请号：US11072312

申请日：2005-03-07

Applicant: Andrew M. Waite ,  Scott Luning ,  Philip A. Fisher

Inventor： Andrew M. Waite ,  Scott Luning ,  Philip A. Fisher

IPC: H01L21/336

CPC classification number: H01L29/78621 ,  H01L29/665 ,  H01L29/66628

Abstract: A method and arrangement for reducing the series resistance of the source and drain in a MOSFET device provides for epitaxially grown regions on top of the source and drain extensions to cover portions of the top surfaces of the silicide regions formed on the substrate. The epitaxial material provides an extra flow path for current to flow through to the silicide from the extension, as well as increasing the surface area between the source/drain and the silicide to reduce the contact resistance between the source/drain and the silicide.

Abstract translation: 用于降低MOSFET器件中的源极和漏极的串联电阻的方法和装置提供了在源极和漏极延伸部的顶部上的外延生长区域，以覆盖形成在衬底上的硅化物区域的顶表面的部分。 外延材料提供了一个额外的流动路径，用于电流从延伸部分流到硅化物，以及增加源极/漏极和硅化物之间的表面积，以减少源极/漏极和硅化物之间的接触电阻。

公开(公告)号：US06949436B2

公开(公告)日：2005-09-27

申请号：US10824428

申请日：2004-04-15

Applicant: James F. Buller ,  David Wu ,  Scott Luning ,  Derick Wristers ,  Daniel Kadosh

Inventor： James F. Buller ,  David Wu ,  Scott Luning ,  Derick Wristers ,  Daniel Kadosh

IPC: H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

Abstract: Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner under a gate electrode sidewall spacer. Embodiments include depositing a conformal oxide layer by decoupled plasma deposition, depositing a conformal nitride layer by decoupled plasma deposition, depositing a spacer layer and then etching.

Abstract translation: 具有改善的晶体管性能的半导体器件通过在栅电极侧壁间隔物下形成复合氧化物/氮化物衬垫来制造。 实施例包括通过解耦等离子体沉积沉积保形氧化物层，通过去耦等离子体沉积沉积共形氮化物层，沉积间隔层然后蚀刻。

公开(公告)号：US06482726B1

公开(公告)日：2002-11-19

申请号：US09690152

申请日：2000-10-17

Applicant: Massud Aminpur ,  David Wu ,  Scott Luning

Inventor： Massud Aminpur ,  David Wu ,  Scott Luning

IPC: H01L213205

CPC classification number: H01L21/28123 ,  H01L29/6659

Abstract: A method is provided, the method including forming a gate dielectric layer above a substrate layer, forming a gate conductor layer above the gate dielectric layer, forming a first hard mask layer above the gate conductor layer, and forming a second hard mask layer above the first hard mask layer. The method also includes forming a trimmed photoresist mask above the second hard mask layer, and forming a patterned hard mask in the second hard mask layer using the trimmed photoresist mask to remove portions of the second hard mask layer, the patterned hard mask having a first dimension. The method further includes forming a selectively etched hard mask in the first hard mask layer by removing portions of the first hard mask layer adjacent the patterned hard mask, the selectively etched hard mask having a second dimension less than the first dimension, and forming a gate structure using the selectively etched hard mask to remove portions of the gate conductor layer above the gate dielectric layer.

Abstract translation: 提供了一种方法，该方法包括在衬底层上方形成栅介质层，在栅极介电层上方形成栅极导体层，在栅极导体层之上形成第一硬掩模层，并形成第二硬掩模层 第一硬掩模层。 该方法还包括在第二硬掩模层之上形成修整的光致抗蚀剂掩模，并且在第二硬掩模层中使用经修剪的光致抗蚀剂掩模形成图案化的硬掩模以去除第二硬掩模层的部分，图案化硬掩模具有第一 尺寸。 该方法还包括通过去除与图案化的硬掩模相邻的第一硬掩模层的部分来形成第一硬掩模层中的选择性蚀刻的硬掩模，该选择性蚀刻的硬掩模具有小于第一尺寸的第二尺寸，以及形成栅极 结构，其使用选择性蚀刻的硬掩模以去除栅极介电层上方的栅极导体层的部分。

公开(公告)号：US06232166B1

公开(公告)日：2001-05-15

申请号：US09187523

申请日：1998-11-06

Applicant: Dong-Hyuk Ju ,  Scott Luning

Inventor： Dong-Hyuk Ju ,  Scott Luning

IPC: H01L218238

CPC classification number: H01L29/66537 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

Abstract: Halo implant regions are formed in a P-channel semiconductor device employing a zero degree tilt angle. N-type impurities are ion implanted to the desired depth in the semiconductor substrate prior to forming P-channel lightly doped source/drain areas. Subsequently, moderately or heavily doped source/drain regions are formed, followed by activation annealing. The halo implants diffuse to form halo structures at the desired location, thereby reducing short channel effects, such as subsurface punchthrough. Other embodiments enable independent control of the junction depths and channel lengths of N- and P-channel transistors, while maintaining high manufacturing throughput.

Abstract translation: 卤素注入区域形成在采用零度倾斜角的P沟道半导体器件中。 在形成P沟道轻掺杂的源极/漏极区之前，将N型杂质离子注入半导体衬底中所需的深度。 随后，形成适度或重掺杂的源极/漏极区，随后进行激活退火。 光晕植入物在期望的位置扩散以形成晕圈结构，从而减少短通道效应，例如地下穿孔。 其他实施例能够独立控制N沟道晶体管和P沟道晶体管的结深度和沟道长度，同时保持高的制造吞吐量。

公开(公告)号：US06180468B2

公开(公告)日：2001-01-30

申请号：US09177774

申请日：1998-10-23

Applicant: Bin Yu ,  Emi Ishida ,  Scott Luning ,  Timothy Thurgate

Inventor： Bin Yu ,  Emi Ishida ,  Scott Luning ,  Timothy Thurgate

IPC: H01L21336

CPC classification number: H01L29/66537 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/6659

Abstract: An ultra-low thermal budget process is provided for channel implant by using a reverse process sequence where a conventional MOS transistor is formed without the channel implant. The originally deposited polysilicon gate is removed, a nitride film deposition and etch is used to form a nitride spacer with a predetermined configuration, and a self-aligned channel implant is performed. After the channel implantation, anneal and super-retrograded doping, the nitride spacer and the gate oxide are removed for subsequent regrowth of a second gate oxide and a polysilicon deposition to form a second polysilicon gate.

Abstract translation: 通过使用反向工艺流程为通道注入提供超低热量预算过程，其中形成常规MOS晶体管而不需要沟道注入。 去除原来沉积的多晶硅栅极，使用氮化物膜沉积和蚀刻来形成具有预定配置的氮化物间隔物，并且执行自对准沟道注入。 在通道注入，退火和超退火掺杂之后，去除氮化物间隔物和栅极氧化物，以便随后的第二栅极氧化物的再生长和多晶硅沉积形成第二多晶硅栅极。

公开(公告)号：US6117719A

公开(公告)日：2000-09-12

申请号：US993060

申请日：1997-12-18

Applicant: Scott Luning ,  Emi Ishida

Inventor： Scott Luning ,  Emi Ishida

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L29/66492 ,  H01L21/2255 ,  H01L29/1045 ,  H01L29/6659

Abstract: Impurities are formed in the active region of a semiconductor substrate by diffusion from a gate electrode sidewall spacer. A gate electrode is formed on a semiconductor substrate with a gate dielectric layer therebetween. Sidewall spacers are formed on the side surfaces of the gate electrode. Dopant atoms are subsequently introduce to transform the spacers into solid dopant sources. Dopant atoms are diffused from the spacers into the semiconductor substrate to form first doped regions.

Abstract translation: 通过从栅电极侧壁间隔物的扩散，在半导体衬底的有源区中形成杂质。 在半导体衬底上形成有栅电介质层的栅电极。 侧壁间隔物形成在栅电极的侧表面上。 随后引入掺杂原子以将间隔物转化为固体掺杂剂源。 掺杂原子从间隔物扩散到半导体衬底中以形成第一掺杂区域。