公开(公告)号：US20060101254A1

公开(公告)日：2006-05-11

申请号：US11296599

申请日：2005-12-06

申请人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

发明人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

IPC分类号： G06F9/44

CPC分类号： G06F9/528 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3857 ,  Y10S707/99953

摘要： One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.

公开(公告)号：US20050273583A1

公开(公告)日：2005-12-08

申请号：US11083263

申请日：2005-03-16

申请人： Paul Caprioli ,  Shailender Chaudhry ,  Marc Tremblay

发明人： Paul Caprioli ,  Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/45 ,  G06F12/08

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857

摘要： One embodiment of the present invention provides a system that facilitates executing a memory barrier (membar) instruction in an execute-ahead processor, wherein the membar instruction forces buffered loads and stores to complete before allowing a following instruction to be issued. During operation in a normal-execution mode, the processor issues instructions for execution in program order. Upon encountering a membar instruction, the processor determines if the load buffer and store buffer contain unresolved loads and stores. If so, the processor defers the membar instruction and executes subsequent program instructions in execute-ahead mode. In execute-ahead mode, instructions that cannot be executed because of an unresolved data dependency are deferred, and other non-deferred instructions are executed in program order. When all stores and loads that precede the membar instruction have been committed to memory from the store buffer and the load buffer, the processor enters a deferred mode and executes the deferred instructions, including the membar instruction, in program order. If all deferred instructions have been executed, the processor returns to the normal-execution mode and resumes execution from the point where the execute-ahead mode left off.

摘要翻译： 本发明的一个实施例提供了一种便于在执行前处理器中执行存储器屏障（membar）指令的系统，其中，在允许执行后续指令之前，该指令强制缓冲的负载和存储完成。 在正常执行模式下的操作期间，处理器以程序顺序发出执行指令。 在遇到一条指令时，处理器确定加载缓冲区和存储缓冲区是否包含未解决的负载和存储。 如果是这样，则处理器延迟膜指令，并以执行模式执行后续的程序指令。 在执行提前模式下，由于未解决的数据依赖关系而无法执行的指令被延迟，并且其他非延迟指令以程序顺序执行。 当存储缓冲区和加载缓冲区之前的所有存储和负载已经提交到存储缓冲区的内存中时，处理器以程序顺序进入延迟模式并执行延迟指令，包括指令指令。 如果所有延迟指令都已执行，则处理器返回到正常执行模式，并从执行方式退出的点恢复执行。

公开(公告)号：US20050223201A1

公开(公告)日：2005-10-06

申请号：US11095644

申请日：2005-03-30

申请人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

发明人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/383 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3863

摘要： One embodiment of the present invention provides a processor that facilitates rapid progress while speculatively executing instructions in scout mode. During normal operation, the processor executes instructions in a normal execution mode. Upon encountering a stall condition, the processor executes the instructions in a scout mode, wherein the instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor. While speculatively executing the instructions in scout mode, the processor maintains dependency information for each register indicating whether or not a value in the register depends on an unresolved data-dependency. If an instruction to be executed in scout mode depends on an unresolved data dependency, the processor executes the instruction as a NOOP so that the instruction executes rapidly without tying up computational resources. The processor also propagates dependency information indicating an unresolved data dependency to a destination register for the instruction.

摘要翻译： 本发明的一个实施例提供了一种在侦察模式下推测性地执行指令时促进快速进展的处理器。 在正常操作期间，处理器以正常执行模式执行指令。 在遇到停顿状态时，处理器以侦察模式执行指令，其中推测性地执行指令以预取将来的负载，但是其中结果未被提交到处理器的架构状态。 当在侦察模式中推测性地执行指令时，处理器维护每个寄存器的依赖性信息，指示寄存器中的值是否取决于未解决的数据依赖性。 如果以侦察模式执行的指令取决于未解决的数据依赖关系，则处理器将该指令执行为NOOP，以使指令快速执行，而不占用计算资源。 处理器还将指示未解决的数据依赖关系的依赖信息传播到指令的目的地寄存器。

公开(公告)号：US20050223194A1

公开(公告)日：2005-10-06

申请号：US11082282

申请日：2005-03-16

申请人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

发明人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn Jacobson

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30061 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3842

摘要： A user is provided with means to sample memory hierarchy via software. This allows a user to enhance memory-level parallelism via software. A status of information needed for execution of a second computer program instruction is read in response to execution of a first computer program instruction. Execution continues with execution of the second computer program instruction upon the status being a first status. Alternatively, a third computer program instruction is executed upon the status being a second status different from the first status. Thus, execution of the first computer program instruction allows control of the memory hierarchy, which in turn give the user control of the memory hierarchy.

摘要翻译： 为用户提供了通过软件对存储器层次结构进行抽样的方法。 这允许用户通过软件来增强内存级并行性。 响应于第一计算机程序指令的执行，读取执行第二计算机程序指令所需的信息的状态。 在状态为第一状态时，继续执行第二计算机程序指令。 或者，在状态是与第一状态不同的第二状态的情况下执行第三计算机程序指令。 因此，第一计算机程序指令的执行允许对存储器层次的控制，这进而使得用户对存储器层级进行控制。

公开(公告)号：US06721944B2

公开(公告)日：2004-04-13

申请号：US09761226

申请日：2001-01-16

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F945

CPC分类号： G06F9/3851 ,  G06F9/3842

摘要： One embodiment of the present invention provides a system that marks memory elements based upon how information retrieved from the memory elements affects speculative program execution. This system operates by allowing a programmer to examine source code that is to be compiled into executable code for a head thread that executes program instructions, and for a speculative thread that executes program instructions in advance of the head thread. During read operations to memory elements by the speculative thread, this executable code generally causes the speculative thread to update status information associated with the memory elements to indicate that the memory elements have been read by the speculative thread. Next, the system allows the programmer to identify a given read operation directed to a given memory element, wherein a given value retrieved from the given memory element during the given read operation does not affect subsequent execution of the speculative thread. The programmer is then allowed to insert a hint into the source code specifying that the speculative thread is not to update status information during the given read operation directed to the given memory element. Next, the system compiles the source code, including the hint, into the executable code, so that during the given read operation, the executable code does not cause the speculative thread to update status information associated with the given memory element to indicate that the given memory element has been read by the speculative thread.

摘要翻译： 本发明的一个实施例提供了一种基于如何从存储器元件检索的信息影响推测程序执行来标记存储器元件的系统。 该系统通过允许程序员检查要编译成用于执行程序指令的头部线程的可执行代码的源代码，以及在头部线程之前执行程序指令的推测线程。 在通过推测线程对存储器元件的读取操作期间，该可执行代码通常导致推测线程更新与存储器元件相关联的状态信息，以指示存储器元件已被推测性线程读取。 接下来，系统允许程序员识别针对给定存储器元件的给定读取操作，其中在给定读取操作期间从给定存储器元件检索的给定值不影响推测线程的后续执行。 然后，程序员可以在源代码中插入提示，指定在给定的给定内存元素的给定读操作期间，推测线程不更新状态信息。 接下来，系统将源代码（包括提示）编译到可执行代码中，使得在给定的读取操作期间，可执行代码不会导致推测线程更新与给定存储器元件相关联的状态信息，以指示给定的 内存元素已被推测线程读取。

公开(公告)号：US06704862B1

公开(公告)日：2004-03-09

申请号：US09591142

申请日：2000-06-09

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F938

CPC分类号： G06F9/3842 ,  G06F9/3861

摘要： One embodiment of the present invention provides a system that supports exception handling through use of a conditional trap instruction. The system supports a head thread that executes program instructions and a speculative thread that speculatively executes program instructions in advance of the head thread. During operation, the system uses the speculative thread to execute code, which includes an instruction that can cause an exception condition. After the instruction is executed, the system determines if the instruction caused the exception condition. If so, the system writes an exception condition indicator to a register. At some time in the future, the system executes a conditional trap instruction which examines a value in the register. If the value in the register is an exception condition indicator, the system executes a trap handling routine to handle the exception condition. Otherwise, the system proceeds with execution of the code. In one embodiment of the present invention, prior to executing the instruction, the system allows a compiler to optimize a program containing the instruction. This optimization process includes scheduling an exception testing instruction associated with the instruction to occupy a free instruction slot following the instruction. This exception testing instruction determines if the instruction causes the exception condition. In one embodiment of the present invention, the trap handling routine triggers a rollback operation to undo operations performed by the speculative thread.

摘要翻译： 本发明的一个实施例提供一种通过使用条件陷阱指令来支持异常处理的系统。 该系统支持执行程序指令的头线程和在头部线程之前推测性地执行程序指令的推测线程。 在运行期间，系统使用推测线程来执行代码，其中包含可能导致异常情况的指令。 执行指令后，系统确定指令是否引起异常情况。 如果是这样，系统会将一个异常状态指示器写入寄存器。 在将来的某个时间，系统执行条件陷阱指令，检查寄存器中的值。 如果寄存器中的值是异常条件指示符，系统将执行陷阱处理例程来处理异常情况。 否则，系统继续执行代码。 在本发明的一个实施例中，在执行指令之前，系统允许编译器优化包含该指令的程序。 该优化处理包括调度与指令相关联的异常测试指令，以占用指令之后的空闲指令槽。 该异常测试指令确定指令是否导致异常情况。 在本发明的一个实施例中，陷阱处理例程触发回滚操作以撤消由推测线程执行的操作。

公开(公告)号：US06430649B1

公开(公告)日：2002-08-06

申请号：US09327398

申请日：1999-06-07

申请人： Shailender Chaudhry ,  Marc Tremblay ,  James M. O'Connor

发明人： Shailender Chaudhry ,  Marc Tremblay ,  James M. O'Connor

IPC分类号： G06F938

CPC分类号： G06F9/3842 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system that enforces dependencies between memory references within a load store unit (LSU) in a processor. When a write request is received in the load store unit, the write request is loaded into a store buffer in the LSU. The write request may include a “watch address” specifying that a subsequent load from the watch address cannot occur before the write request completes. Note that the watch address is not necessarily the same as the destination address of the write operation. When a read request is received in the load store unit, the read request is loaded into a load buffer of the LSU. The system determines if the read request is directed to the same address as a matching watch address in the store buffer. If so, the system waits for the write request associated with the matching watch address to complete before completing the read request. In one embodiment of the present invention, if the read request is directed to the same address as a matching write request in the store buffer, the system completes the read request by returning a data value contained in the matching write request without going out to memory. In one embodiment of the present invention, the system provides an executable code write instruction that specifies the watch address.

摘要翻译： 本发明的一个实施例提供了一种在处理器中的加载存储单元（LSU）内实现存储器引用之间的依赖性的系统。 当在加载存储单元中接收到写请求时，写请求被加载到LSU中的存储缓冲器中。 写请求可以包括指定来自监视地址的后续加载在写请求完成之前不会发生的“监视地址”。 请注意，手表地址不一定与写入操作的目标地址相同。 当在加载存储单元中接收到读请求时，读请求被加载到LSU的加载缓冲器中。 系统确定读请求是否与存储缓冲区中匹配的监视地址指向相同的地址。 如果是这样，则在完成读取请求之前，系统等待与匹配的监视地址相关联的写入请求完成。 在本发明的一个实施例中，如果读请求针对与存储缓冲器中的匹配写请求相同的地址，则系统通过返回包含在匹配写请求中的数据值来完成读请求，而不用外存 。 在本发明的一个实施例中，系统提供了一个指定监视地址的可执行代码写入指令。

公开(公告)号：US08447931B1

公开(公告)日：2013-05-21

申请号：US11173110

申请日：2005-07-01

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F12/00

CPC分类号： G06F9/30141 ,  G06F9/383 ,  G06F9/3867 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1075 ,  G11C8/08 ,  G11C2207/107 ,  G11C2207/108

摘要： One embodiment of the present invention provides a processor that supports multiple-issue execution. This processor includes a register file, which contains an array of memory cells, wherein the memory cells contain bits for architectural registers of the processor. The register file also includes multiple read ports and multiple write ports to support multiple-issue execution. During operation, if multiple read ports simultaneously read from a given register, the register file is configured to: read each bit of the given register out of the array of memory cells through a single bitline associated with the bit; and to use a driver located outside of the array of memory cells to drive the bit to the multiple read ports. In this way, each memory cell only has to drive a single bitline (instead of multiple bitlines) during a multiple-port read operation, thereby allowing memory cells to use smaller and more power-efficient drivers for read operations.

摘要翻译： 本发明的一个实施例提供一种支持多次执行的处理器。 该处理器包括一个寄存器文件，该寄存器文件包含一个存储单元阵列，其中存储单元包含处理器结构寄存器的位。 注册文件还包括多个读取端口和多个写入端口，以支持多次执行。 在操作期间，如果从给定寄存器同时读取多个读取端口，则寄存器文件被配置为：通过与该位相关联的单个位线，将给定寄存器的每个位从存储器单元阵列中读出; 并使用位于存储器单元阵列之外的驱动器将该位驱动到多个读取端口。 以这种方式，每个存储器单元仅在多端口读取操作期间仅驱动单个位线（而不是多个位线），从而允许存储器单元使用较小且更省电的驱动器进行读取操作。

公开(公告)号：US07930695B2

公开(公告)日：2011-04-19

申请号：US11418652

申请日：2006-05-05

申请人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

发明人： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

IPC分类号： G06F9/46

CPC分类号： G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857

摘要： One embodiment of the present invention provides a system that synchronizes threads on a multi-threaded processor. The system starts by executing instructions from a multi-threaded program using a first thread and a second thread. When the first thread reaches a predetermined location in the multi-threaded program, the first thread executes a Start-Transactional-Execution (STE) instruction to commence transactional execution, wherein the STE instruction specifies a location to branch to if transactional execution fails. During the subsequent transactional execution, the first thread accesses a mailbox location in memory (which is also accessible by the second thread) and then executes instructions that cause the first thread to wait. When the second thread reaches a second predetermined location in the multi-threaded program, the second thread signals the first thread by accessing the mailbox location, which causes the transactional execution of the first thread to fail, thereby causing the first thread to resume non-transactional execution from the location specified in the STE instruction. In this way, the second thread can signal to the first thread without the first thread having to poll a shared variable.

摘要翻译： 本发明的一个实施例提供了一种在多线程处理器上同步线程的系统。 系统通过使用第一个线程和第二个线程执行来自多线程程序的指令来启动。 当第一线程到达多线程程序中的预定位置时，第一线程执行开始 - 事务执行（STE）指令以开始事务执行，其中STE指令指定分支到事务执行失败的位置。 在随后的事务执行期间，第一个线程访问存储器中的邮箱位置（也可由第二个线程访问），然后执行使第一个线程等待的指令。 当第二线程到达多线程程序中的第二预定位置时，第二线程通过访问邮箱位置来发信号通知第一线程，这导致第一线程的事务性执行失败，从而使第一线程恢复为非线程， 从STE指令中指定的位置进行事务执行。 以这种方式，第二线程可以向第一线程发信号，而第一线程不必轮询共享变量。

公开(公告)号：US20100049957A1

公开(公告)日：2010-02-25

申请号：US12197629

申请日：2008-08-25

申请人： Marc Tremblay ,  Shailender Chaudhry

发明人： Marc Tremblay ,  Shailender Chaudhry

IPC分类号： G06F9/30

CPC分类号： G06F9/3889 ,  G06F9/3804 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

摘要： Embodiments of the present invention provide a system that executes program code in a processor. The system starts by executing the program code in a normal mode using a primary strand while concurrently executing the program code ahead of the primary strand using a subordinate strand in a scout mode. Upon resolving a branch using the subordinate strand, the system records a resolution for the branch in a speculative branch resolution table. Upon subsequently encountering the branch using the primary strand, the system uses the recorded resolution from the speculative branch resolution table to predict a resolution for the branch for the primary strand. Upon determining that the resolution of the branch was mispredicted for the primary strand, the system determines that the subordinate strand mispredicted the branch. The system then recovers the subordinate strand to the branch and restarts the subordinate strand executing the program code.

摘要翻译： 本发明的实施例提供一种在处理器中执行程序代码的系统。 系统通过使用主链在正常模式下执行程序代码，同时使用侦察模式中的从属线同时执行主链前面的程序代码来开始。 在使用下级线解析分支时，系统在推测分支分辨率表中记录分支的分辨率。 在随后使用主链遇到分支时，系统使用来自推测性分支分辨率表的记录分辨率来预测主股的分支的分辨率。 在确定分支的决议对于主要股份进行了错误估计时，系统确定下级股错误地预测了分行。 系统然后将下级线路恢复到分支，并重新启动执行程序代码的下级线程。