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41.发明申请Method for Forming a Test Pad and Method for Performing Array Test Using the Test Pad 有权用于形成测试垫的方法和使用测试垫执行阵列测试的方法公开(公告)号：US20160341789A1
公开(公告)日：2016-11-24
申请号：US14423113
申请日：2015-01-06
IPC: G01R31/28 , H01L29/786 , H01L27/12 , H01L21/77 , H01L21/66
CPC classification number: G01R31/2884 , G01R31/28 , H01L21/77 , H01L22/14 , H01L22/32 , H01L27/12 , H01L29/78672
Abstract: The disclosure is related to a method for forming a test pad between adjacent transistors regions, comprising forming a plurality of transistor regions in an array on a glass substrate, wherein each of the transistor region comprises a first transistor region and a second transistor region arranged oppositely; and forming a plurality of test pads between the first transistor region and the second transistor region. The disclosure is further related to a method for array test on the adjacent transistor regions using the test pad formed by the above method. A common test pad formed between the adjacent transistor regions of each transistor region group is employed by the disclosure to perform array test on the adjacent transistor regions. Thus the size of the adjacent fringe region of each transistor region may be reduced to facilitate achieving narrow frame of a display.
Abstract translation: 本发明涉及在相邻晶体管区域之间形成测试焊盘的方法，包括在玻璃衬底上形成阵列中的多个晶体管区域，其中每个晶体管区域包括相对布置的第一晶体管区域和第二晶体管区域 ; 以及在所述第一晶体管区域和所述第二晶体管区域之间形成多个测试焊盘。 本公开还涉及使用通过上述方法形成的测试垫的相邻晶体管区域上的阵列测试方法。 通过本公开采用在每个晶体管区域组的相邻晶体管区域之间形成的公共测试焊盘对相邻晶体管区域进行阵列测试。 因此，可以减小每个晶体管区域的相邻条纹区域的尺寸，以便于实现显示器的窄帧。
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42.发明申请BONDING PAD STRUCTURE OF LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME 有权液晶显示器的结合片结构及其制造方法公开(公告)号：US20160274405A1
公开(公告)日：2016-09-22
申请号：US14375629
申请日：2014-07-07
Inventor： Peng DU
IPC: G02F1/1345 , G02F1/1343 , G02F1/1362 , G02F1/1368
CPC classification number: G02F1/13458 , G02F1/13439 , G02F1/136227 , G02F1/1368 , G02F2001/13606
Abstract: A bonding pad structure of liquid crystal display, having a plurality of bonding pads formed at part of the upper surface of the edge area of the substrate, and an overcoat layer with one side being inclined surface and positioned at the other part of upper surface of the bonding pad. The inclined surface is formed when patterning the overcoat layer covering the bonding pad by using the mask with gradient transmittance and removing the overcoat layer formed at part of the upper surface of the bonding pad. Also discloses a manufacturing method of the bonding pad structure of liquid crystal display.
Abstract translation: 一种液晶显示器的接合焊盘结构，其具有形成在基板的边缘区域的上表面的一部分处的多个接合焊盘，以及一侧是倾斜表面并且位于该基板的上表面的另一部分的外涂层 接合垫。 通过使用具有梯度透射率的掩模来图案化覆盖焊盘的外涂层时，形成倾斜表面，并且去除在焊盘的上表面的一部分处形成的外涂层。 还公开了一种液晶显示器的焊盘结构的制造方法。
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公开(公告)号：US20160240120A1
公开(公告)日：2016-08-18
申请号：US14379803
申请日：2014-05-16
Inventor： Peng DU
CPC classification number: G09G3/006 , G09G3/3648 , G09G3/3696 , G09G2330/04 , G09G2330/12
Abstract: The embodiments of the present invention disclose a test circuit and a display panel, the test circuit comprises a test circuit first terminal, a test circuit second terminal, a test signal line, a voltage signal line, a switching transistor and a first electrostatic discharge protection circuit; the test signal line transmits the test signal, one end is connected with the first terminal, the other end is respectively connected with the switching transistor and the common electrode; the switching transistor is connected with the signal line, according to the received voltage signal on or off to conduct or cut off the test signal with signal line; the first electrostatic discharge protection circuit is respectively connected with the test signal line and signal line. To implement the embodiments, providing a test circuit and a display panel which occupy small space, it is conducive to the narrow border display panel design.
Abstract translation: 本发明的实施例公开了测试电路和显示面板，测试电路包括测试电路第一端子，测试电路第二端子，测试信号线，电压信号线，开关晶体管和第一静电放电保护 电路 测试信号线传输测试信号，一端与第一端连接，另一端分别与开关晶体管和公共电极连接; 开关晶体管与信号线连接，根据接收的电压信号打开或关闭，用信号线导通或切断测试信号; 第一静电放电保护电路分别与测试信号线和信号线相连。 为了实现这些实施例，提供占据小空间的测试电路和显示面板，有利于窄边框显示面板的设计。
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44.发明申请LTPS TFT Having Dual Gate Structure and Method for Forming LTPS TFT 有权具有双栅结构的LTPS TFT和形成LTPS TFT的方法公开(公告)号：US20160133473A1
公开(公告)日：2016-05-12
申请号：US14415607
申请日：2014-11-14
Inventor： Xiaoxiao WANG , Hsiang Chih HSIAO , Peng DU , Chang-I SU , Hongyuan XU , Bo SUN
IPC: H01L21/28 , H01L29/423 , H01L29/66 , H01L29/49 , H01L27/12 , H01L29/786
CPC classification number: H01L21/28114 , H01L21/28035 , H01L27/1222 , H01L27/1288 , H01L29/42384 , H01L29/4908 , H01L29/6675 , H01L29/78603 , H01L29/78648 , H01L29/78672
Abstract: The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.
Abstract translation: 本发明提出了一种具有双栅极结构的低温多晶硅薄膜晶体管和形成低温多晶硅薄膜晶体管的方法。 低温多晶硅薄膜晶体管包括：基板，设置在基板上的阻挡层中的一个或多个图案化非晶硅（a-Si）层，用于形成底栅，设置在势垒层上的NMOS 和设置在阻挡层上的PMOS。 NMOS包括作为顶栅的图案化栅电极（GE）层，并且由一个或多个图案化a-Si层形成的图案化GE层和底栅形成双栅结构。 本发明提出了具有更稳定的I-V特性，更好的驱动能力，低功耗和更高的产量的低温多晶硅薄膜晶体管。
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公开(公告)号：US20190204754A1
公开(公告)日：2019-07-04
申请号：US15110067
申请日：2016-06-23
Inventor： Wen DAI , Peng DU , Jianjian YING
IPC: G03F7/20 , G03F1/50 , G02F1/1337
Abstract: The disclosure discloses a method for exposing a transparent substrate, including: fixing relative positions of a first mask, a second mask and the transparent substrate; exposing various regions of the transparent substrate by light with different polarization directions generated by the first mask and the second mask respectively. By the method above, the disclosure can simplify the process, reduce the period and improve efficiency of production.
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Patent Agency Ranking
公开(公告)号：US20190156774A1
公开(公告)日：2019-05-23
申请号：US15118882
申请日：2016-07-11
Inventor： Peng DU
IPC: G09G3/36
Abstract: The invention provides a display panel and a gate driving circuit thereof including multiple stages of gate driving units. Each gate driving unit includes: a first pulling control circuit for outputting a first pulling control signal at a first node; a first pulling circuit for generating a gate driving signal according to the first pulling control signal and a first clock signal; a second pulling control circuit for outputting a second pulling control signal; and a second pulling circuit for pulling levels at the first node and an output terminal of the gate driving signal according to the second pulling control signal. A frequency of the second pulling control signal is lower than a frequency of the first clock signal but higher than a refresh rate of the display panel. The invention can prevent thin film transistor characteristic drift and thereby improve reliability of the gate driving unit.
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公开(公告)号：US20180261169A1
公开(公告)日：2018-09-13
申请号：US14906352
申请日：2015-12-30
Inventor： Peng DU
IPC: G09G3/36 , G02F1/1362
CPC classification number: G09G3/3607 , G02F1/136286 , G09G3/3614 , G09G2300/0426 , G09G2300/0452 , G09G2300/0823 , G09G2310/0213
Abstract: An array substrate with a data line sharing structure is described. The array substrate comprises a source driver; a plurality of scan lines for receiving a scan signal wherein the scan lines comprise a plurality of odd scan lines and even scan lines; and a plurality of data lines for correspondingly receiving a data signal of the source driver wherein the data lines comprise a plurality of odd data lines and even data lines which are sequentially arranged; wherein the scan lines and the data lines are insulatedly interlaced in an array, each pixel region comprises a data line and at least two scan lines, each pixel region is composed of a plurality of sub-pixels with different color types correspondingly, and the drive polarities of the sub-pixels with the same color types in different pixel regions comprises a positive polarity and a negative polarity based on the data signal.
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公开(公告)号：US20180254011A1
公开(公告)日：2018-09-06
申请号：US15971219
申请日：2018-05-04
Inventor： Peng DU , MING-HUNG SHIH , CHIH-TSUNG KANG , JE-HAO HSU , Qibiao LV
IPC: G09G3/36 , G02F1/1362 , G02F1/1368 , G02F1/1343
CPC classification number: G09G3/3607 , G02F1/134309 , G02F1/13624 , G02F1/136286 , G02F1/1368 , G02F2001/134345 , G02F2201/121 , G09G3/3655 , G09G3/3688 , G09G2300/0426 , G09G2300/0447
Abstract: A thin film transistor (TFT) array substrate and a display panel are provided. The TFT array substrate includes multiple pixels arranged in an array. Each pixel includes first through third sub-pixels sequentially arranged along a first direction. The first through third sub-pixels are connected to a same scan line. The TFT array substrate further includes first through third data lines sequentially arranged along the first direction. The first through third data lines respectively are for driving the first through third sub-pixels. The first sub-pixel includes first and second areas, the second sub-pixel includes third and fourth areas, and the third sub-pixel includes fifth and sixth areas, arranged along a second direction. A voltage difference between a sub-pixel electrode in the sixth area and a common electrode is different from a voltage difference between a sub-pixel electrode in the fifth area and the common electrode.
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公开(公告)号：US20180233098A1
公开(公告)日：2018-08-16
申请号：US15509499
申请日：2017-02-15
Inventor： Peng DU
CPC classification number: G09G3/3677 , G02F1/13 , G02F1/13306 , G09G2300/0408 , G09G2310/0264 , G09G2310/0286 , G09G2310/08
Abstract: A gate driver on array (GOA) and a liquid crystal display are disclosed. The GOA circuit includes a plurality of cascaded GOA units and a plurality of pull-down maintaining circuits. The cascaded GOA units are configured for respectively outputting gate driving signals of first level signals to charge corresponding horizontal scanning lines within a display area when being controlled by a plurality of clock signals. Each of the pull-down maintaining circuits corresponds to at least two cascaded GOA units, and each of the pull-down maintaining circuits is configured for maintaining the corresponding at least two cascaded GOA units to output second level signals as the gate driving signals during a non-operation period. As described above, the disclosure can reduce the amount of the pull-down maintaining circuits, so as to decrease the width of the layout of the GOA circuit to meet the need to design a narrow-frame liquid crystal display.
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公开(公告)号：US20180196316A1
公开(公告)日：2018-07-12
申请号：US15123665
申请日：2016-07-11
Inventor： Jianjian YING , Peng DU , Wen DAI
IPC: G02F1/1337
CPC classification number: G02F1/133788 , G02F1/1337 , G02F1/133753 , G02F2001/133757
Abstract: The present application discloses a method of performing photo alignment to a liquid crystal panel and a mask, the method including: disposing a mask in one side of a liquid crystal panel, the mask including at least two regions, the two regions makes incident lights passed and generating emission lights with different polarization directions respectively; making the incident light passed through the mask, to generate the emission lights with different polarization direction, and perform a photo alignment to the different regions of the liquid crystal panel. By the approach above, the process of the photo alignment is changed in the present application, thereby reducing the time of the photo alignment process and increase productivity.
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