公开(公告)号：US20120052661A1

公开(公告)日：2012-03-01

申请号：US13213130

申请日：2011-08-19

申请人： Shinya SASAGAWA ,  Hiroshi FUJIKI ,  Shinobu FURUKAWA ,  Hidekazu MIYAIRI

发明人： Shinya SASAGAWA ,  Hiroshi FUJIKI ,  Shinobu FURUKAWA ,  Hidekazu MIYAIRI

IPC分类号： H01L21/20

CPC分类号： H01L21/32137 ,  H01L29/6675 ,  H01L29/66765 ,  H01L29/78663 ,  H01L29/78669 ,  H01L29/78672 ,  H01L29/78678 ,  H01L29/78687

摘要： A method for etching is provided in which the etching selectivity of an amorphous semiconductor film to a crystalline semiconductor film is high. Part of a stacked semiconductor film in which an amorphous semiconductor film is provided on a crystalline semiconductor film is etched using a mixed gas of a Br-based gas, a F-based gas, and an oxygen gas, so that part of the crystalline semiconductor film provided in the stacked semiconductor film is exposed. Reduction in the film thickness of the exposed portion can be suppressed by performing the etching in such a manner. Moreover, when etching for forming a back channel portion of a thin film transistor is performed with the method for etching, favorable electric characteristics of the thin film transistor can be obtained. An insulating layer is preferably provided over the thin film transistor.

摘要翻译： 提供了一种用于蚀刻的方法，其中非晶半导体膜对结晶半导体膜的蚀刻选择性高。 使用Br基气体，F系气体和氧气的混合气体蚀刻在结晶半导体膜上设置非晶半导体膜的层叠半导体膜的一部分，使得部分结晶半导体 提供在堆叠的半导体膜中的膜被暴露。 可以通过以这种方式进行蚀刻来抑制曝光部分的膜厚度的降低。 此外，当利用蚀刻方法进行用于形成薄膜晶体管的背沟道部分的蚀刻时，可以获得薄膜晶体管的良好的电特性。 绝缘层优选设置在薄膜晶体管的上方。

公开(公告)号：US20110272816A1

公开(公告)日：2011-11-10

申请号：US13187746

申请日：2011-07-21

申请人： Shinya SASAGAWA ,  Satoru OKAMOTO ,  Shigeharu MONOE

发明人： Shinya SASAGAWA ,  Satoru OKAMOTO ,  Shigeharu MONOE

IPC分类号： H01L23/48 ,  H05K1/11

CPC分类号： H01L27/3276 ,  G02F2001/13629 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L51/0021 ,  H01L51/0023 ,  H01L51/5281 ,  H01L2924/0002 ,  H05K3/06 ,  H05K2203/0315 ,  H05K2203/0346 ,  H05K2203/095 ,  H05K2203/1476 ,  H01L2924/00

摘要： A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed. According to the present invention, a method for manufacturing a wiring over a substrate is provided that comprises the steps of: forming a first conductive layer over an insulating surface; forming a first mask pattern over the first conductive layer; forming a second mask pattern by etching the first mask pattern under a first condition, simultaneously, forming a second conductive layer having a side having an angle of inclination cross-sectionally by etching the first conductive layer; and forming a third conductive layer and a third mask pattern by etching the second conductive layer and the second mask pattern under a second condition; wherein a selective ratio under the first condition of the first conductive layer to the first mask pattern is in a range of 0.25 to 4, and a selective ratio under the second condition of the second conductive layer to the second mask pattern is larger than that under the first condition.

摘要翻译： 公开了一种能够减少布线之间的颗粒的基板上的布线和用于制造布线的方法。 还公开了一种能够防止布线之间的大的差异和配线间的凹陷之间的布线之间的短路的布线和布线的制造方法。 此外，还公开了能够防止由于布线或颗粒的边缘处的应力导致的绝缘层中的裂纹的基板上的布线以及布线的制造方法。 根据本发明，提供了一种用于在衬底上制造布线的方法，包括以下步骤：在绝缘表面上形成第一导电层; 在所述第一导电层上形成第一掩模图案; 通过在第一条件下蚀刻第一掩模图案形成第二掩模图案，同时通过蚀刻第一导电层形成具有横截面为倾斜角的一侧的第二导电层; 以及通过在第二条件下蚀刻所述第二导电层和所述第二掩模图案来形成第三导电层和第三掩模图案; 其中在第一导电层与第一掩模图案的第一条件下的选择比在0.25至4的范围内，并且在第二导电层与第二掩模图案的第二条件下的选择比大于 第一个条件。

公开(公告)号：US20100019337A1

公开(公告)日：2010-01-28

申请号：US12575910

申请日：2009-10-08

申请人： Shinya SASAGAWA ,  Shinya Hasegawa ,  Hidekazu Takahashi ,  Tatsuya Arao

发明人： Shinya SASAGAWA ,  Shinya Hasegawa ,  Hidekazu Takahashi ,  Tatsuya Arao

IPC分类号： H01L31/0232 ,  H01L31/0352

CPC分类号： H01L31/035281 ,  H01L21/32136 ,  H01L21/32137 ,  H01L27/14643 ,  Y02E10/50

摘要： An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane.

公开(公告)号：US20070278606A1

公开(公告)日：2007-12-06

申请号：US11737477

申请日：2007-04-19

申请人： Shinya SASAGAWA ,  Shinya HASEGAWA ,  Hidekazu TAKAHASHI ,  Tatsuya ARAO

发明人： Shinya SASAGAWA ,  Shinya HASEGAWA ,  Hidekazu TAKAHASHI ,  Tatsuya ARAO

IPC分类号： H01L31/075 ,  H01L31/18

CPC分类号： H01L31/035281 ,  H01L21/32136 ,  H01L21/32137 ,  H01L27/14643 ,  Y02E10/50

摘要： An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane.

摘要翻译： 本发明的目的是提供一种具有不同锥角的侧面的光电转换元件，该光电转换元件逐步进行光电转换层的蚀刻。 与pn光电二极管相比，pin光电二极管具有高响应速度，但是具有大的暗电流的缺点。 认为暗电流的一个原因是通过在蚀刻中产生并沉积在光电转换层的侧表面上的蚀刻残余物导电。 光电转换元件的泄漏电流通过形成侧表面具有两个不同的锥形形状的结构而降低，通常具有均匀的表面，使得光电转换层具有p层的侧表面和侧表面 的n层，它们不在同一平面。

公开(公告)号：US20100176461A1

公开(公告)日：2010-07-15

申请号：US12731824

申请日：2010-03-25

申请人： Shinya SASAGAWA

发明人： Shinya SASAGAWA

IPC分类号： H01L29/49

CPC分类号： H01L21/76804 ,  H01L23/485 ,  H01L27/124 ,  H01L29/41733 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for easily manufacturing a semiconductor device in which variation in thickness or disconnection of a source electrode or a drain electrode is prevented is proposed. A semiconductor device includes a semiconductor layer formed over an insulating substrate; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; an opening which reaches the semiconductor layer and is formed at least in the first insulating layer and the second insulating layer; and a step portion formed at a side surface of the second insulating layer in the opening.

摘要翻译： 提出一种容易制造半导体器件的方法，其中防止了源电极或漏电极的厚度变化或断开。 半导体器件包括形成在绝缘基板上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 至少形成在所述第一绝缘层和所述第二绝缘层中的至少形成在所述半导体层上的开口部; 以及形成在所述开口中的所述第二绝缘层的侧表面处的台阶部。

公开(公告)号：US20080237876A1

公开(公告)日：2008-10-02

申请号：US12046881

申请日：2008-03-12

申请人： Shinya SASAGAWA

发明人： Shinya SASAGAWA

IPC分类号： H01L23/52 ,  H01L21/28

CPC分类号： H01L21/76804 ,  H01L23/485 ,  H01L27/124 ,  H01L29/41733 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for easily manufacturing a semiconductor device in which variation in thickness or disconnection of a source electrode or a drain electrode is prevented is proposed A semiconductor device includes a semiconductor layer formed over an insulating substrate; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; an opening which reaches the semiconductor layer and is formed at least in the first insulating layer and the second insulating layer; and a step portion formed at a side surface of the second insulating layer in the opening.

摘要翻译： 提出一种容易制造其中防止源电极或漏电极的厚度变化或断开的半导体器件的方法。一种半导体器件包括形成在绝缘基板上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 至少形成在所述第一绝缘层和所述第二绝缘层中的至少形成在所述半导体层上的开口部; 以及形成在所述开口中的所述第二绝缘层的侧表面处的台阶部。

公开(公告)号：US20120288993A1

公开(公告)日：2012-11-15

申请号：US13466664

申请日：2012-05-08

申请人： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Hiroshi FUJIKI

发明人： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Hiroshi FUJIKI

IPC分类号： H01L21/34

CPC分类号： H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

摘要： To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl2, BCl3, SiCl4, or the like. In formation of a source electrode layer and a drain electrode layer, a conductive layer on and in contact with the In—Sn—Zn—O-based semiconductor layer can be selectively etched with little removal of the In—Sn—Zn—O-based semiconductor layer with the use of a gas containing oxygen or fluorine in addition to a gas containing chlorine.

摘要翻译： 为了建立包括In-Sn-Zn-O类半导体的半导体器件的制造中的加工技术。 通过使用含氯气体如Cl 2，BCl 3，SiCl 4等的干蚀刻来选择性地蚀刻In-Sn-Zn-O系半导体层。 在形成源极电极层和漏电极层时，可以选择性地蚀刻与In-Sn-Zn-O系半导体层接触的导电层，同时很少去除In-Sn-Zn-O系半导体层， 除了含有氯的气体之外，还使用含有氧或氟的气体。

公开(公告)号：US20120270375A1

公开(公告)日：2012-10-25

申请号：US13446022

申请日：2012-04-13

申请人： Shinya SASAGAWA ,  Akihiro ISHIZUKA

发明人： Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC分类号： H01L21/336

CPC分类号： H01L29/4236 ,  H01L29/42384 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

摘要： To provide a semiconductor device which prevents defects and achieves miniaturization. A projecting portion or a trench (a groove portion) is formed in an insulating layer and a channel formation region of a semiconductor layer is provided in contact with the projecting portion or the trench, so that the channel formation region is extended in a direction perpendicular to a substrate. Thus, miniaturization of the transistor can be achieved and an effective channel length can be extended. In addition, before formation of the semiconductor layer, an upper-end corner portion of the projecting portion or the trench with which the semiconductor layer is in contact is subjected to round chamfering, so that a thin semiconductor layer can be formed with good coverage.

摘要翻译： 提供一种防止缺陷并实现小型化的半导体器件。 在绝缘层中形成突出部分或沟槽（沟槽部分），并且半导体层的沟道形成区域设置成与突出部分或沟槽接触，使得沟道形成区域在垂直方向上延伸 到基底。 因此，可以实现晶体管的小型化并且可以延长有效的沟道长度。 此外，在形成半导体层之前，突出部分的上端拐角部分或与半导体层接触的沟槽进行圆形倒角，从而可以形成具有良好覆盖的薄半导体层。

公开(公告)号：US20120267624A1

公开(公告)日：2012-10-25

申请号：US13446028

申请日：2012-04-13

申请人： Atsuo ISOBE ,  Toshinari SASAKI ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

发明人： Atsuo ISOBE ,  Toshinari SASAKI ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC分类号： H01L29/24 ,  H01L21/34

CPC分类号： H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02667 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696

摘要： An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body, whereby the channel formation region is extended in a three dimensional direction (a direction perpendicular to a substrate). Thus, it is possible to miniaturize a transistor and to extend an effective channel length of the transistor. Further, an upper end corner portion of the projecting structural body, where a top surface and a side surface of the projecting structural body intersect with each other, is curved, and the oxide semiconductor layer is formed to include a crystal having a c-axis perpendicular to the curved surface.

摘要翻译： 绝缘层设置有突出的结构体，并且设置与突出结构体接触的氧化物半导体层的沟道形成区域，由此沟道形成区域沿三维方向（垂直于衬底的方向）延伸 ）。 因此，可以使晶体管小型化并且延长晶体管的有效沟道长度。 此外，突出结构体的顶表面和侧表面彼此相交的突出结构体的上端角部弯曲，并且氧化物半导体层形成为包括具有c轴的晶体 垂直于曲面。

公开(公告)号：US20110207269A1

公开(公告)日：2011-08-25

申请号：US13026520

申请日：2011-02-14

申请人： Shinya SASAGAWA ,  Masashi TSUBUKU ,  Hitoshi NAKAYAMA ,  Daigo SHIMADA

发明人： Shinya SASAGAWA ,  Masashi TSUBUKU ,  Hitoshi NAKAYAMA ,  Daigo SHIMADA

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L21/32136 ,  H01L21/32139 ,  H01L29/66969 ,  H01L29/7869

摘要： A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.

摘要翻译： 晶体管通过以下方法制造：包括：形成第一布线层; 形成第一绝缘膜以覆盖所述第一布线层; 在所述第一绝缘膜上形成半导体层; 在半导体层上形成导电膜; 并且对所述导电膜进行蚀刻的至少两个步骤以形成彼此分离的第二布线层，其中所述两个蚀刻步骤至少包括在导电膜的蚀刻速率为 高于半导体层的蚀刻速率，以及在导电膜和半导体层的蚀刻速率高于第一蚀刻工艺的蚀刻速率的条件下进行的第二蚀刻工艺。