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公开(公告)号：US08754483B2
公开(公告)日：2014-06-17
申请号：US13169081
申请日：2011-06-27
IPC分类号： H01L29/788
CPC分类号： H01L21/76895 , H01L21/823475 , H04L45/58 , H04L49/15 , H04L49/45
摘要： Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks.
摘要翻译： 本发明的实施例提供一种结构。 该结构包括多个场效应晶体管，其具有形成在半导体衬底顶部上的栅极叠层，该栅叠层具有形成在其侧壁上的隔离层; 以及直接形成在半导体衬底的顶部上并将多个场效应晶体管之一的至少一个源极/漏极互连到多个场效应中的另一个的至少一个源极/漏极的一个或多个导电触头 晶体管，其中所述一个或多个导电触点是具有低于所述栅极堆叠的高度的高度的低轮廓局部互连的一部分。
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42.发明授权Mask free protection of work function material portions in wide replacement gate electrodes 有权在宽的替代栅电极中，无功能保护功能材料部分公开(公告)号：US08629511B2
公开(公告)日：2014-01-14
申请号：US13471852
申请日：2012-05-15
IPC分类号： H01L27/088
CPC分类号： H01L29/401 , E21B43/305 , E21B47/122 , H01L21/823431 , H01L21/823456 , H01L21/845 , H01L27/088 , H01L27/0886 , H01L27/1211
摘要： In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.
摘要翻译： 在替代栅极方案中，在形成栅极电介质层之后，功函数材料层完全填充窄栅极沟槽，同时不填充宽栅极沟槽。 介电材料层在功函数材料层上沉积并平面化，随后凹入以形成覆盖宽栅极沟槽内的功函数材料层的水平部分的介电材料部分。 使用介电材料部分作为蚀刻掩模的一部分来凹入功函数材料层以形成功函数材料部分。 将导电材料沉积并平坦化以形成栅极导体部分，并且沉积和平坦化介电材料以形成栅极盖电介质。
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公开(公告)号：US20130026635A1
公开(公告)日：2013-01-31
申请号：US13191999
申请日：2011-07-27
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76841 , H01L21/76843 , H01L21/76847 , H01L21/76877 , H01L21/76882 , H01L2924/0002 , H01L2924/00
摘要： A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region. The copper regions containing the different impurities levels can be achieved utilizing a combination of physical vapor deposition of a copper region having a low impurity level (i.e., less than 20 ppm) and copper reflow, with electroplating another copper region having a high impurity level (i.e., 100 ppm or greater).
摘要翻译： 提供了包含在相同开口内具有不同杂质水平的铜区域的混合互连结构。 在一个实施例中，互连结构包括具有位于其中的至少一个开口的图案化电介质材料。 双材料衬垫至少位于所述至少一个开口内的图案化电介质材料的侧壁上。 所述结构还包括具有位于所述至少一个开口的底部区域内的第一杂质水平的第一铜区域和具有位于所述至少一个开口的顶部区域内的第二杂质水平的第二铜区域和位于所述第一铜 地区。 根据本公开，第一铜区域的第一杂质水平不同于第二铜区域的第二杂质水平。 可以利用具有低杂质水平（即小于20ppm）的铜区域和铜回流的物理气相沉积与电镀另一个具有高杂质水平的铜区域的组合来实现含有不同杂质水平的铜区域 即100ppm以上）。
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44.发明授权Borderless interconnect line structure self-aligned to upper and lower level contact vias 有权无边界互连线结构自对准到上层和下层接触孔公开(公告)号：US08299625B2
公开(公告)日：2012-10-30
申请号：US12899911
申请日：2010-10-07
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L21/76885 , H01L21/76897 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
摘要翻译： 金属层沉积在其上暴露下面的金属通孔的顶表面的平坦表面上。 图案化金属层以形成至少一个金属块，其具有要形成的金属线的水平横截面积和要形成的至少一个上覆的金属通孔。 下面的金属通孔的每个上部凹陷在位于正上方的金属块的区域的外部。 至少一个金属块的上部被光刻地图案化以形成集成线和通孔结构，其包括具有基本上恒定的宽度的金属线和至少一个覆盖的金属通孔，其具有相同的基本上恒定的宽度并且与金属线无边界地对准 。 沉积和平坦化上层电介质材料层，使得至少一个上覆金属通孔的顶表面被暴露。
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公开(公告)号：US08609534B2
公开(公告)日：2013-12-17
申请号：US12890941
申请日：2010-09-27
IPC分类号： H01L21/4763
CPC分类号： H01L23/5256 , H01L21/76805 , H01L21/76807 , H01L21/76831 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.
摘要翻译： 使用位于金属层顶部的双镶嵌结构来提供高编程效率电熔丝。 双镶嵌结构包括图案化电介质材料，其具有位于下面的通孔开口上方并连接到下面的通孔开口的线路开口。 通孔开口位于顶部并连接到金属层。 双镶嵌结构还包括线路开口和通孔开口内的导电特征。 电介质间隔物也存在于线路开口和通孔开口内。 介电间隔物存在于图案化电介质材料的垂直侧壁上，并将导电特征与图案化电介质材料分开。 在线路开口和通孔开口内的电介质间隔物的存在减少了形成导电特征的区域。 因此，提供了节省空间的高编程效率电熔丝。
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公开(公告)号：US20130320411A1
公开(公告)日：2013-12-05
申请号：US13488581
申请日：2012-06-05
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78 , H01L21/28247 , H01L21/76834 , H01L21/76897 , H01L29/66545
摘要： A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region.
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公开(公告)号：US08492270B2
公开(公告)日：2013-07-23
申请号：US12885665
申请日：2010-09-20
申请人： Shom Ponoth , David V Horak , Elbert E Huang , Sivananda K Kanakasabapathy , Charles W Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V Horak , Elbert E Huang , Sivananda K Kanakasabapathy , Charles W Koburger, III , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53266 , H01L21/32139 , H01L21/76885 , H01L21/76897 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.
摘要翻译： 为诸如集成电路的互连结构提供了用于形成与不透明层下面的特征对准的结构的方法。 在一个实施例中，该方法包括在第一层上形成不透明层，第一层具有映射到其中的至少一个特征的表面形貌，其中不透明层被形成为使得表面形貌在不透明层上可见。 通过参考这种表面形貌，第二特征被定位并形成在不透明层中。
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公开(公告)号：US20130112462A1
公开(公告)日：2013-05-09
申请号：US13290557
申请日：2011-11-07
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76847 , H01L21/76849 , H01L21/76877 , H01L21/76882 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T29/49124 , H01L2924/00
摘要： A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy cap, and a capping layer.
摘要翻译： 包括金属合金覆盖层的金属互连结构及其制造方法。 互连特征内的原始沉积的合金覆盖层元件将扩散到并分离到金属互连的顶表面上。 金属合金覆盖材料沉积在回流铜表面上，并且不物理地与互连特征的侧壁接触。 因此，互连结构中的残余合金元素的电阻率冲击降低。 也就是说，在金属互连结构的特征内部存在合金元素的减少。 金属互连结构包括具有凹陷线的介电层，侧壁上的衬垫材料，铜材料，合金盖和覆盖层。
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公开(公告)号：US20130069161A1
公开(公告)日：2013-03-21
申请号：US13233064
申请日：2011-09-15
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L29/42372 , H01L21/28247 , H01L21/76834 , H01L21/7685 , H01L21/76856 , H01L21/76888 , H01L21/76897 , H01L29/495 , H01L29/517 , H01L29/78
摘要： Methods of forming an integrated circuit structure utilizing a selectively formed and at least partially oxidized metal cap over a gate, and associated structures. In one embodiment, a method includes providing a precursor structure including a transistor having a metal gate; forming an etch stop layer over an exposed portion of the metal gate; at least partially oxidizing the etch stop layer; and forming a dielectric layer over the at least partially oxidized etch stop layer.
摘要翻译： 在栅极上利用选择性地形成和至少部分氧化的金属盖形成集成电路结构的方法以及相关联的结构。 在一个实施例中，一种方法包括提供包括具有金属栅极的晶体管的前体结构; 在所述金属栅极的暴露部分上形成蚀刻停止层; 至少部分氧化所述蚀刻停止层; 以及在所述至少部分氧化的蚀刻停止层上形成电介质层。
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公开(公告)号：US20120326237A1
公开(公告)日：2012-12-27
申请号：US13169081
申请日：2011-06-27
IPC分类号： H01L29/772
CPC分类号： H01L21/76895 , H01L21/823475 , H04L45/58 , H04L49/15 , H04L49/45
摘要： Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks.
摘要翻译： 本发明的实施例提供一种结构。 该结构包括多个场效应晶体管，其具有形成在半导体衬底顶部上的栅极叠层，该栅叠层具有形成在其侧壁上的隔离层; 以及直接形成在半导体衬底的顶部上并将多个场效应晶体管之一的至少一个源极/漏极互连到多个场效应中的另一个的至少一个源极/漏极的一个或多个导电触点 晶体管，其中所述一个或多个导电触点是具有低于所述栅极堆叠的高度的高度的低轮廓局部互连的一部分。
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