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公开(公告)号：US20130320411A1
公开(公告)日：2013-12-05
申请号：US13488581
申请日：2012-06-05
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78 , H01L21/28247 , H01L21/76834 , H01L21/76897 , H01L29/66545
摘要： A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region.
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2.发明授权Electrical isolation structures for ultra-thin semiconductor-on-insulator devices 有权用于超薄绝缘体上半导体器件的电气隔离结构公开(公告)号：US08629008B2
公开(公告)日：2014-01-14
申请号：US13348018
申请日：2012-01-11
IPC分类号： H01L21/02
CPC分类号： H01L29/0653 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78603 , H01L29/78654
摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.
摘要翻译： 在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。 随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。 平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。 通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。 沉积至少一个接触电介质层。 可以在接触通孔内形成与手柄基板电隔离的结构的接触。
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3.发明申请ELECTRICAL ISOLATION STRUCTURES FOR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR DEVICES 有权用于超薄半导体绝缘体器件的电气隔离结构公开(公告)号：US20130175622A1
公开(公告)日：2013-07-11
申请号：US13348018
申请日：2012-01-11
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78603 , H01L29/78654
摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.
摘要翻译： 在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。 随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。 平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。 通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。 沉积至少一个接触电介质层。 可以在接触通孔内形成与手柄基板电隔离的结构的接触。
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公开(公告)号：US08383490B2
公开(公告)日：2013-02-26
申请号：US13191540
申请日：2011-07-27
IPC分类号： H01L21/76
CPC分类号： H01L29/0653 , H01L21/76283 , H01L21/76832 , H01L21/76834 , H01L21/76897 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/665 , H01L29/66628 , H01L29/7841 , H01L29/7843 , H01L29/78609
摘要： After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.
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公开(公告)号：US20130026570A1
公开(公告)日：2013-01-31
申请号：US13191540
申请日：2011-07-27
IPC分类号： H01L29/772 , H01L23/48 , H01L21/28
CPC分类号： H01L29/0653 , H01L21/76283 , H01L21/76832 , H01L21/76834 , H01L21/76897 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/665 , H01L29/66628 , H01L29/7841 , H01L29/7843 , H01L29/78609
摘要： After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.
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公开(公告)号：US08987070B2
公开(公告)日：2015-03-24
申请号：US13611182
申请日：2012-09-12
IPC分类号： H01L21/00 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/31144 , H01L21/76283 , H01L21/84 , H01L29/06 , H01L29/66772 , H01L29/78654
摘要： A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.
摘要翻译： 具有隔离区域的半导体基板及其形成方法。 该方法包括以下步骤：提供具有衬底层，掩埋氧化物（BOX），绝缘体上硅（SOI）层，衬垫氧化物层和衬垫氮化物层的衬底，形成浅沟槽区，蚀刻衬垫 氧化层以形成耳朵并蚀刻BOX层以形成底切，在浅沟槽区域上沉积衬垫，在浅沟槽区域的表面上沉积软掩模，填充浅沟槽区域，蚀刻软掩模，使得它 凹陷到BOX层的顶部，在某些区域蚀刻衬垫，去除软掩模，以及填充和抛光浅沟槽区域。 当触点不对准时，衬垫防止半导体器件的短路。
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公开(公告)号：US20140061794A1
公开(公告)日：2014-03-06
申请号：US13598080
申请日：2012-08-29
申请人： Kangguo Cheng , Balasubramanian S. Haran , Shom Ponoth , Theodorus E. Standaert , Tenko Yamashita
发明人： Kangguo Cheng , Balasubramanian S. Haran , Shom Ponoth , Theodorus E. Standaert , Tenko Yamashita
CPC分类号： H01L29/7851 , H01L29/0653 , H01L29/1083 , H01L29/161 , H01L29/165 , H01L29/66803 , H01L29/7848 , H01L29/7849
摘要： A finFET with self-aligned punchthrough stopper and methods of manufacture are disclosed. The method includes forming spacers on sidewalls of a gate structure and fin structures of a finFET device. The method further includes forming a punchthrough stopper on exposed sidewalls of the fin structures, below the spacers. The method further includes diffusing dopants from the punchthrough stopper into the fin structures. The method further includes forming source and drain regions adjacent to the gate structure and fin structures.
摘要翻译： 公开了具有自对准穿通塞子的finFET和制造方法。 该方法包括在栅极结构的侧壁和finFET器件的翅片结构上形成间隔物。 该方法还包括在隔片的下方在翅片结构的暴露的侧壁上形成穿通止动件。 该方法还包括将穿透止动器的掺杂剂扩散到鳍结构中。 该方法还包括形成与栅极结构和鳍结构相邻的源区和漏区。
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公开(公告)号：US20140001555A1
公开(公告)日：2014-01-02
申请号：US13537141
申请日：2012-06-29
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Shom Ponoth , Theodorus E. Standaert , Tenko Yamashita
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Shom Ponoth , Theodorus E. Standaert , Tenko Yamashita
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0649 , H01L21/76229 , H01L21/76232 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/41766 , H01L29/78 , H01L29/7838
摘要： A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.
摘要翻译： 制造绝缘体上硅（SOI）半导体器件的方法包括将底切隔离沟槽蚀刻成SOI衬底，所述SOI衬底包括底部衬底，形成在底部衬底上的掩埋氧化物（BOX）层，以及顶部 SOI层，其形成在BOX层上，其中底切隔离沟槽延伸穿过顶部SOI层和BOX层并进入底部衬底，使得底切绝缘沟槽的一部分位于BOX层下方的底部衬底中。 底切隔离槽填充有包括绝缘材料的底切填充物以形成底切隔离区域。 在与底切隔离区相邻的顶部SOI层上形成场效应晶体管（FET）器件，其中底切隔离区延伸在FET的源极/漏极区的下方。
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公开(公告)号：US20130344677A1
公开(公告)日：2013-12-26
申请号：US13531780
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
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公开(公告)号：US20130341754A1
公开(公告)日：2013-12-26
申请号：US13531654
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
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