公开(公告)号：US10580492B2

公开(公告)日：2020-03-03

申请号：US16107282

申请日：2018-08-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11521 ,  H01L27/11524 ,  G06N3/06 ,  G06N3/063 ,  G11C16/24

Abstract: A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate disposed over a second channel region portion. A plurality of bit lines each extends along one of the columns and is electrically connected to the drain regions of a first group of one or more of the memory cells in the column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the column. A plurality of source lines each is electrically connected to the source regions of the memory cells in one of the columns or rows. A plurality of gate lines each is electrically connected to the second gates of memory cells in one of the columns or rows.

公开(公告)号：US20200035310A1

公开(公告)日：2020-01-30

申请号：US16590798

申请日：2019-10-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C11/54 ,  G11C16/04 ,  G06N3/08 ,  G11C16/30 ,  G11C16/26

Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.

公开(公告)号：US10534554B2

公开(公告)日：2020-01-14

申请号：US15784025

申请日：2017-10-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  H01L21/78 ,  H01L27/11521 ,  H01L29/423 ,  H01L23/00

Abstract: Apparatus, and an associated method, for enhancing security and preventing hacking of a flash memory device. The apparatus and method use a random number to offset the read or write address in a memory cell. The random number is generated by determining the leakage current of memory cells. In another embodiment, random data can be written or read in parallel to thwart hackers from determining contents of data being written or read by monitoring sense amplifiers.

公开(公告)号：US10460811B2

公开(公告)日：2019-10-29

申请号：US16387377

申请日：2019-04-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/04

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

公开(公告)号：US20190206486A1

公开(公告)日：2019-07-04

申请号：US16213860

申请日：2018-12-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Hieu Van Tran ,  Nhan Do

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C2211/5641

Abstract: A memory device includes memory cells each configured to produce an output current during a read operation. Circuitry is configured to, for each of the memory cells, generate a read value based on the output current of the memory cell. Circuitry is configured to, for each of the memory cells, multiply the read value for the memory cell by a multiplier to generate a multiplied read value, wherein the multiplier for each of the memory cells is different from the multipliers for any others of the memory cells. Circuitry is configured to sum the multiplied read values. The read values can be electrical currents, electrical voltages or numerical values. Alternatively, added constant values can be used instead of multipliers. The multipliers or constants can be applied to read currents from individual cells, or read currents on entire bit lines.

公开(公告)号：US10340010B2

公开(公告)日：2019-07-02

申请号：US15238681

申请日：2016-08-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/32

Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.

公开(公告)号：US20190172543A1

公开(公告)日：2019-06-06

申请号：US16271673

申请日：2019-02-08

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Xinjie Guo ,  Farnood Merrikh Bayat ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari

IPC: G11C16/34 ,  H01L27/11524 ,  H01L29/788 ,  G11C16/04 ,  G11C8/14 ,  H01L27/11521 ,  G11C16/26 ,  G11C16/14 ,  G11C16/10 ,  H01L27/11558 ,  G11C7/18

CPC classification number: G11C16/3431 ,  G11C7/18 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11558 ,  H01L29/7881

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

公开(公告)号：US20190088329A1

公开(公告)日：2019-03-21

申请号：US16107282

申请日：2018-08-21

Applicant: Silicon Storage Technology, Inc

Inventor： Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11521 ,  G06N3/06

Abstract: A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate disposed over a second channel region portion. A plurality of bit lines each extends along one of the columns and is electrically connected to the drain regions of a first group of one or more of the memory cells in the column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the column. A plurality of source lines each is electrically connected to the source regions memory cells in one of the columns or rows. A plurality of gate lines each is electrically connected to the second gates of memory cells in one of the columns or rows.

公开(公告)号：US20180286486A1

公开(公告)日：2018-10-04

申请号：US15905720

申请日：2018-02-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Mark Reiten

IPC: G11C16/24 ,  H01L27/11521 ,  G11C16/04 ,  G11C16/28

CPC classification number: G11C16/24 ,  G06F7/588 ,  G11C16/0425 ,  G11C16/22 ,  G11C16/28 ,  H01L27/11521 ,  H01L29/42328

Abstract: A memory device that generates a unique identifying number, and includes a plurality of memory cells and a controller. Each of the memory cells includes first and second regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the first and second regions, a floating gate disposed over and insulated from a first portion of the channel region, and a select gate disposed over and insulated from a second portion of the channel region. The controller is configured to apply one or more positive voltages to the first regions of the memory cells while the memory cells are in a subthreshold state for generating leakage current through each of the channel regions, measure the leakage currents, and generate a number based on the measured leakage currents.

公开(公告)号：US20180268912A1

公开(公告)日：2018-09-20

申请号：US15987735

申请日：2018-05-23

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Xinjie Guo ,  Farnood Merrikh Bayat ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari

IPC: G11C16/34 ,  H01L27/11558 ,  H01L27/11521 ,  G11C16/26 ,  G11C16/10 ,  G11C16/14

CPC classification number: G11C16/3431 ,  G11C7/18 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11558 ,  H01L29/7881

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.