公开(公告)号：US10381359B2

公开(公告)日：2019-08-13

申请号：US15701357

申请日：2017-09-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Feng Zhou

IPC: H01L27/11531 ,  H01L27/11524 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11521

Abstract: A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.

公开(公告)号：US20190080754A1

公开(公告)日：2019-03-14

申请号：US16119416

申请日：2018-08-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong ,  Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Numerous embodiments of methods for writing to a resistive random access memory (RRAM) cell are disclosed. In one embodiment, the system verifies if a current through the RRAM cell exceeds a threshold value, and if it does not, the system executes a concurrent write-while-verify operation. In another embodiment, the system verifies if current through the RRAM cell has reached a target value, and if it has not, the system executes a write operation and then verifies the write operation using a current comparison.

公开(公告)号：US09721958B2

公开(公告)日：2017-08-01

申请号：US15003659

申请日：2016-01-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Chun-Ming Chen ,  Man-Tang Wu ,  Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L21/336 ,  H01L27/11524 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11536 ,  H01L21/306

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11536 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

公开(公告)号：US20170125603A1

公开(公告)日：2017-05-04

申请号：US15294174

申请日：2016-10-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Jeng-Wei Yang ,  Nhan Do

IPC: H01L29/788 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/7883 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66825

Abstract: A non-volatile memory cell that includes a silicon substrate, source and drain regions formed in the silicon substrate (where a channel region of the substrate is defined between the source and drain regions), a metal floating gate disposed over and insulated from a first portion of the channel region, a metal control gate disposed over and insulated from the metal floating gate, a polysilicon erase gate disposed over and insulated from the source region, and a polysilicon word line gate disposed over and insulated from a second portion of the channel region.

公开(公告)号：US20160181517A1

公开(公告)日：2016-06-23

申请号：US14582089

申请日：2014-12-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Nhan Do ,  Hieu Van Tran ,  Hung Quoc Nguyen

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/16 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/50 ,  G11C2213/52 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1273 ,  H01L45/146

Abstract: A memory device (and method of making and using the memory device) includes a first electrode of conductive material, a second electrode of conductive material, and a layer transition metal oxide material that includes first and second elongated portions meeting each other at a sharp corner. Each of the first and second elongated portions is disposed between and in electrical contact with the first and second electrodes.

Abstract translation: 存储器件（以及制造和使用存储器件的方法）包括导电材料的第一电极，导电材料的第二电极和层过渡金属氧化物材料，其包括在锐角处相互相遇的第一和第二细长部分 。 第一和第二细长部分中的每一个设置在第一和第二电极之间并与之电接触。