公开(公告)号：US20120202335A1

公开(公告)日：2012-08-09

申请号：US13300787

申请日：2011-11-21

申请人： Dong-Sik Lee ,  Jang-Hyun You ,  Jee-Hoon Han ,  Young-Woo Park ,  Sung-Hoi Hur ,  Sang-Ick Joo

发明人： Dong-Sik Lee ,  Jang-Hyun You ,  Jee-Hoon Han ,  Young-Woo Park ,  Sung-Hoi Hur ,  Sang-Ick Joo

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/76229 ,  H01L21/764

摘要： A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

摘要翻译： 制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。 沟槽和其间的有源区延伸到衬底的第一和第二器件区域。 牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。 选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分，以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将沟槽中的绝缘层保持在有源区 在第二设备区域中。 还讨论了相关的方法和设备。

公开(公告)号：US07977730B2

公开(公告)日：2011-07-12

申请号：US12385664

申请日：2009-04-15

申请人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954

摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

摘要翻译： 一种形成存储器件的方法，其中可以在衬底上形成第一绝缘体层和电荷俘获层，并且可以对第一绝缘体层和电荷俘获层中的至少一个进行图案化以形成图案化区域。 可以在图案化区域上形成第二绝缘层和导电层，并且可以对导电层，第二绝缘体层，电荷俘获层和第一绝缘体层中的一个或多个进行图案化以形成串选择线，接地选择线， 在基板上的串选择线和地选择线之间的多个字线，低压栅电极和多个不同厚度的绝缘体。 所形成的存储器件可以是例如具有SONOS栅极结构的NAND型非易失性存储器件。

公开(公告)号：US20110101439A1

公开(公告)日：2011-05-05

申请号：US12987440

申请日：2011-01-10

申请人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

发明人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

IPC分类号： H01L29/78

CPC分类号： H01L21/76895 ,  H01L21/76877 ,  H01L23/485

摘要： An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.

摘要翻译： 半导体器件的互连结构包括设置在半导体衬底上的级间绝缘层。 第一接触结构穿透层间绝缘层。 第二接触构造穿透层间绝缘层。 金属互连将第一接触结构连接到层间绝缘层上的第二接触结构。 第一接触构造包括依次堆叠的第一和第二插塞，并且第二接触构造包括第二插塞。

公开(公告)号：US07585710B2

公开(公告)日：2009-09-08

申请号：US11638775

申请日：2006-12-14

申请人： Min-Cheol Park ,  Sung-Hoi Hur

发明人： Min-Cheol Park ,  Sung-Hoi Hur

IPC分类号： H01L29/72

CPC分类号： H01L21/76877 ,  H01L21/28525 ,  H01L29/66628 ,  H01L29/78

摘要： Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode. An insulating layer may be formed on the semiconductor substrate including the first and second impurity doped regions, and first and second holes may be formed in the insulating layer, with the first and second holes respectively exposing portions of the first and second impurity doped regions. In addition, first and second epitaxial semiconductor layers may be formed in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate. Related devices are also discussed.

摘要翻译： 形成电子器件的方法可以包括在半导体衬底上形成栅电极，以及在栅电极的相对侧上形成半导体衬底的第一和第二杂质掺杂区。 可以在包括第一和第二杂质掺杂区域的半导体衬底上形成绝缘层，并且可以在绝缘层中形成第一和第二孔，其中第一和第二孔分别暴露第一和第二杂质掺杂区域的部分。 此外，可以在半导体衬底的第一和第二杂质掺杂区域的暴露部分上的相应的第一和第二孔中形成第一和第二外延半导体层。 还讨论了相关设备。

公开(公告)号：US20090206392A1

公开(公告)日：2009-08-20

申请号：US12385664

申请日：2009-04-15

申请人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954

摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

摘要翻译： 一种形成存储器件的方法，其中可以在衬底上形成第一绝缘体层和电荷俘获层，并且可以对第一绝缘体层和电荷俘获层中的至少一个进行图案化以形成图案化区域。 可以在图案化区域上形成第二绝缘层和导电层，并且可以对导电层，第二绝缘体层，电荷俘获层和第一绝缘体层中的一个或多个进行图案化以形成串选择线，接地选择线， 在基板上的串选择线和地选择线之间的多个字线，低压栅电极和多个不同厚度的绝缘体。 所形成的存储器件可以是例如具有SONOS栅极结构的NAND型非易失性存储器件。

公开(公告)号：US07501322B2

公开(公告)日：2009-03-10

申请号：US11558634

申请日：2006-11-10

申请人： Sung-Hoi Hur ,  Jung-Dal Choi

发明人： Sung-Hoi Hur ,  Jung-Dal Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.

摘要翻译： 半导体存储器件包括其中具有沟槽的半导体衬底。 第一和第二栅极图案形成在与沟槽相邻的衬底的表面上，其相应的一个位于沟槽的相应的相对侧上。 在第一栅极图案和第二栅极图案之间的衬底中形成分离源极/漏极区域，使得分离源极/漏极区域被沟槽分开。 分离源极/漏极区域包括在第一栅极图案和沟槽之间的第一源极/漏极子区域和在第二栅极图案和沟槽之间并与第一源极/漏极子区域间隔开的第二源极/漏极子区域。 在从第一源/漏区域到第二源极/漏极子区域的沟槽周围延伸的衬底中形成连接区域。 还讨论了相关方法。

公开(公告)号：US07285815B2

公开(公告)日：2007-10-23

申请号：US11336751

申请日：2006-01-20

申请人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

发明人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

IPC分类号： H01L29/76

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

摘要： An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.

摘要翻译： EEPROM包括用于限定多个有源区的器件隔离层，跨越有源区延伸的一对控制栅极和跨越有源区延伸并插入在控制栅极图案之间的一对选择栅极图案。 浮动栅极图案形成在跨越有源区域的控制栅极图案延伸的交叉区域上。 在选择栅极图案跨越有源区域延伸的交叉区域上形成下部栅极图案。 栅极间电介质图案设置在控制栅极图案和浮置栅极图案之间，并且虚设电介质图案设置在选择栅极图案和下部栅极图案之间。 虚拟介质图案基本上平行于选择栅极图案，并且与选择栅极图案的一个侧壁自对准以重叠选择栅极图案的预定宽度。

公开(公告)号：US07223659B2

公开(公告)日：2007-05-29

申请号：US11048852

申请日：2005-02-03

申请人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L21/8247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954

摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

摘要翻译： 一种形成存储器件的方法，其中可以在衬底上形成第一绝缘体层和电荷俘获层，并且可以对第一绝缘体层和电荷俘获层中的至少一个进行图案化以形成图案化区域。 可以在图案化区域上形成第二绝缘层和导电层，并且可以对导电层，第二绝缘体层，电荷俘获层和第一绝缘体层中的一个或多个进行图案化以形成串选择线，接地选择线， 在基板上的串选择线和地选择线之间的多个字线，低压栅电极和多个不同厚度的绝缘体。 所形成的存储器件可以是例如具有SONOS栅极结构的NAND型非易失性存储器件。

公开(公告)号：US20070090466A1

公开(公告)日：2007-04-26

申请号：US11638775

申请日：2006-12-14

申请人： Min-Cheol Park ,  Sung-Hoi Hur

发明人： Min-Cheol Park ,  Sung-Hoi Hur

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L21/76877 ,  H01L21/28525 ,  H01L29/66628 ,  H01L29/78

摘要： Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode. An insulating layer may be formed on the semiconductor substrate including the first and second impurity doped regions, and first and second holes may be formed in the insulating layer, with the first and second holes respectively exposing portions of the first and second impurity doped regions. In addition, first and second epitaxial semiconductor layers may be formed in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate. Related devices are also discussed.

摘要翻译： 形成电子器件的方法可以包括在半导体衬底上形成栅电极，以及在栅电极的相对侧上形成半导体衬底的第一和第二杂质掺杂区。 可以在包括第一和第二杂质掺杂区域的半导体衬底上形成绝缘层，并且可以在绝缘层中形成第一和第二孔，其中第一和第二孔分别暴露第一和第二杂质掺杂区域的部分。 此外，可以在半导体衬底的第一和第二杂质掺杂区域的暴露部分上的相应的第一和第二孔中形成第一和第二外延半导体层。 还讨论了相关设备。

公开(公告)号：US20060124988A1

公开(公告)日：2006-06-15

申请号：US11291142

申请日：2005-11-30

申请人： Sung-Hoi Hur ,  Jung-Dal Choi ,  Kyeong-Tae Kim ,  Jong-Ho Park ,  Jae-Duk Lee ,  Ki-Nam Kim

发明人： Sung-Hoi Hur ,  Jung-Dal Choi ,  Kyeong-Tae Kim ,  Jong-Ho Park ,  Jae-Duk Lee ,  Ki-Nam Kim

IPC分类号： H01L21/82 ,  H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor memory device is fabricated by forming an active region protruding from a semiconductor substrate, forming an isolation layer on the substrate adjacent opposing sidewalls of the active region, and forming a floating gate electrode on a surface of the active region between the opposing sidewalls thereof. The floating gate electrode is formed to extend beyond edges of the surface of the active region onto the isolation layer. A surface of the floating gate electrode adjacent the active region defines a plane, and the isolation layer is confined between the plane and the substrate. A control gate electrode is formed on a surface of the floating gate electrode opposite the active region. The control gate electrode may be formed to extend along sidewalls of the floating gate electrode towards the substrate beyond the plane defined by the surface of the floating gate electrode adjacent the active region. Related devices are also discussed.

摘要翻译： 半导体存储器件通过形成从半导体衬底突出的有源区域形成，在邻近有源区域的相对侧壁的衬底上形成隔离层，以及在其相对侧壁之间的有源区域的表面上形成浮栅电极 。 浮栅电极被形成为延伸超过有源区表面的边缘到隔离层上。 邻近有源区的浮栅电极的表面限定了一个平面，隔离层被限制在平面和衬底之间。 控制栅电极形成在浮动栅电极的与有源区相对的表面上。 控制栅电极可以被形成为沿着浮置栅电极的侧壁朝着衬底延伸超过由邻近有源区的浮栅的表面限定的平面。 还讨论了相关设备。