公开(公告)号：US20070252194A1

公开(公告)日：2007-11-01

申请号：US11790047

申请日：2007-04-23

申请人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L27/108 ,  H01L21/8247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954

摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

公开(公告)号：US07538385B2

公开(公告)日：2009-05-26

申请号：US11790047

申请日：2007-04-23

申请人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954

摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

公开(公告)号：US20050152176A1

公开(公告)日：2005-07-14

申请号：US11048852

申请日：2005-02-03

申请人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/115 ,  G11C11/24

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954

摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

公开(公告)号：US07977730B2

公开(公告)日：2011-07-12

申请号：US12385664

申请日：2009-04-15

申请人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954

摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

摘要翻译： 一种形成存储器件的方法，其中可以在衬底上形成第一绝缘体层和电荷俘获层，并且可以对第一绝缘体层和电荷俘获层中的至少一个进行图案化以形成图案化区域。 可以在图案化区域上形成第二绝缘层和导电层，并且可以对导电层，第二绝缘体层，电荷俘获层和第一绝缘体层中的一个或多个进行图案化以形成串选择线，接地选择线， 在基板上的串选择线和地选择线之间的多个字线，低压栅电极和多个不同厚度的绝缘体。 所形成的存储器件可以是例如具有SONOS栅极结构的NAND型非易失性存储器件。

公开(公告)号：US20090206392A1

公开(公告)日：2009-08-20

申请号：US12385664

申请日：2009-04-15

申请人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954

摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

摘要翻译： 一种形成存储器件的方法，其中可以在衬底上形成第一绝缘体层和电荷俘获层，并且可以对第一绝缘体层和电荷俘获层中的至少一个进行图案化以形成图案化区域。 可以在图案化区域上形成第二绝缘层和导电层，并且可以对导电层，第二绝缘体层，电荷俘获层和第一绝缘体层中的一个或多个进行图案化以形成串选择线，接地选择线， 在基板上的串选择线和地选择线之间的多个字线，低压栅电极和多个不同厚度的绝缘体。 所形成的存储器件可以是例如具有SONOS栅极结构的NAND型非易失性存储器件。

公开(公告)号：US07223659B2

公开(公告)日：2007-05-29

申请号：US11048852

申请日：2005-02-03

申请人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L21/8247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954

摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

摘要翻译： 一种形成存储器件的方法，其中可以在衬底上形成第一绝缘体层和电荷俘获层，并且可以对第一绝缘体层和电荷俘获层中的至少一个进行图案化以形成图案化区域。 可以在图案化区域上形成第二绝缘层和导电层，并且可以对导电层，第二绝缘体层，电荷俘获层和第一绝缘体层中的一个或多个进行图案化以形成串选择线，接地选择线， 在基板上的串选择线和地选择线之间的多个字线，低压栅电极和多个不同厚度的绝缘体。 所形成的存储器件可以是例如具有SONOS栅极结构的NAND型非易失性存储器件。

公开(公告)号：US08085592B2

公开(公告)日：2011-12-27

申请号：US12356123

申请日：2009-01-20

申请人： Sung-Won Yun ,  Seung-Hyun Moon ,  Jong-Sun Sel ,  Yoo-Cheol Shin ,  Ki-Hwan Choi ,  Jae-Sung Sim

发明人： Sung-Won Yun ,  Seung-Hyun Moon ,  Jong-Sun Sel ,  Yoo-Cheol Shin ,  Ki-Hwan Choi ,  Jae-Sung Sim

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/04 ,  G11C29/804

摘要： Operation methods of charge-trap flash memory devices having an unused memory cell for data storage and a normal memory cell used for data storage are discussed. The operation method may include selecting the unused memory cell, and programming the unused memory cell to have a predetermined threshold voltage. The charge-trap flash memory device may thus be provided with improved reliability by interrupting erasure stress to unused memory cells.

摘要翻译： 讨论了具有用于数据存储的未使用存储单元和用于数据存储的常规存储单元的充电陷阱闪存器件的操作方法。 操作方法可以包括选择未使用的存储器单元，以及将未使用的存储单元编程为具有预定的阈值电压。 因此，可以通过中断对未使用的存储器单元的擦除应力来提供充电陷阱闪存器件的可靠性。

公开(公告)号：US20100264481A1

公开(公告)日：2010-10-21

申请号：US12827549

申请日：2010-06-30

申请人： Yoo-Cheol Shin ,  Jung-Dal Choi

发明人： Yoo-Cheol Shin ,  Jung-Dal Choi

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： Nonvolatile memory devices and methods of fabricating the same are provided. A semiconductor substrate is provided having a cell field region and a high-voltage field region. Device isolation films are provided on the substrate. The device isolation films define active regions of the substrate. A cell gate-insulation film and a cell gate-conductive film are provided on the cell field region of the substrate including the device isolation films. A high-voltage gate-insulation film and a high-voltage gate-conductive film are provided on the high-voltage field region of the substrate including the device isolation films. The device isolation film on the high-voltage field region of the substrate is at least partially recessed to provide a groove therein.

摘要翻译： 提供非易失性存储器件及其制造方法。 提供具有单元场区域和高电压场区域的半导体基板。 器件隔离膜设置在衬底上。 器件隔离膜定义衬底的有源区。 在包括器件隔离膜的衬底的电池区域上设置电池栅极绝缘膜和电池栅极导电膜。 在包括器件隔离膜的衬底的高压场区域上设置高压栅极绝缘膜和高压栅极导电膜。 衬底的高电压场区域上的器件隔离膜至少部分地凹入以在其中提供沟槽。

公开(公告)号：US20060239077A1

公开(公告)日：2006-10-26

申请号：US11279607

申请日：2006-04-13

申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/107 ,  G11C16/12 ,  G11C16/3445

摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.

摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压 到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。 在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。 在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

公开(公告)号：US07881114B2

公开(公告)日：2011-02-01

申请号：US12340250

申请日：2008-12-19

申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/10

CPC分类号： G11C16/0483 ,  G11C16/107 ,  G11C16/12 ,  G11C16/3445

摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.

摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压 到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。 在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。 在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。