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103 条记录 (耗时 0.033 秒)

    Built-in self-test circuit for voltage controlled oscillators
    41.
    发明授权
    Built-in self-test circuit for voltage controlled oscillators 有权
    用于压控振荡器的内置自检电路

    公开(公告)号：US08729968B2

    公开(公告)日：2014-05-20

    申请号：US13103571

    申请日：2011-05-09

    申请人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H03L5/00

    CPC分类号： G01R31/2824

    摘要： A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

    摘要翻译： 用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。 射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。 此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。 另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

    Clock and data recovery using LC voltage controlled oscillator and delay locked loop
    42.
    发明授权
    Clock and data recovery using LC voltage controlled oscillator and delay locked loop 有权
    使用LC压控振荡器和延迟锁定环的时钟和数据恢复

    公开(公告)号：US08588358B2

    公开(公告)日：2013-11-19

    申请号：US13045788

    申请日：2011-03-11

    申请人： Chan-Hong Chern ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Fu-Lung Hsueh

    发明人： Chan-Hong Chern ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Fu-Lung Hsueh

    IPC分类号： H04L7/00

    CPC分类号： H04L7/033 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/113 ,  H04L7/0337

    摘要： A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.

    摘要翻译： 时钟和数据恢复（CDR）电路包括被配置为产生具有时钟频率的时钟信号的电感器 - 电容器压控振荡器（LCVCO）。 延迟锁定环（DLL）被配置为从LCVCO接收时钟信号并生成多个时钟相位。 电荷泵配置为控制LCVCO。 相位检测器被配置为从DLL接收数据输入和多个时钟相位，并且控制第一电荷泵以便对准数据输入和多个时钟相位的数据沿。

    Low minimum power supply voltage level shifter
    43.
    发明授权
    Low minimum power supply voltage level shifter 有权
    低最小电源电压电平转换器

    公开(公告)号：US08493124B2

    公开(公告)日：2013-07-23

    申请号：US12843479

    申请日：2010-07-26

    申请人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Ming-Chieh Huang ,  Chih-Chang Lin

    发明人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Ming-Chieh Huang ,  Chih-Chang Lin

    IPC分类号： H03L5/00

    CPC分类号： H03K19/018521

    摘要： A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.

    摘要翻译： 电平移位器包括一个PMOS和两个NMOS晶体管。 第一NMOS晶体管的源极耦合到低电源电压。 输入信号耦合到第一NMOS晶体管的栅极和第二NMOS晶体管的源极。 输入信号具有高达第一电源电压的电压电平。 PMOS晶体管的源极耦合到高于第一电源电压的第二电源电压。 输出信号耦合在PMOS和第一NMOS晶体管之间。 第一NMOS晶体管被布置为当输入信号为逻辑1时下拉输出信号，并且第二NMOS晶体管被布置为使得PMOS晶体管能够以第二电源电压将输出信号上拉至逻辑1， 输入信号为逻辑0。

    Level shifters having diode-connected devices for input-output interfaces
    44.
    发明授权
    Level shifters having diode-connected devices for input-output interfaces 有权
    电平移位器具有用于输入 - 输出接口的二极管连接器件

    公开(公告)号：US08436671B2

    公开(公告)日：2013-05-07

    申请号：US12859456

    申请日：2010-08-19

    申请人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chih-Chang Lin ,  Yuwen Swei ,  Ming-Chieh Huang

    发明人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chih-Chang Lin ,  Yuwen Swei ,  Ming-Chieh Huang

    IPC分类号： H03L5/00

    CPC分类号： H03K3/02 ,  H03K19/018521 ,  H03K19/018528

    摘要： A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.

    摘要翻译： 电平移位器包括输入节点，输出节点，上拉晶体管，下拉晶体管以及耦合在上拉晶体管和下拉晶体管之间的至少一个二极管连接器件。 电平移位器被布置为耦合到高电源电压，以在输入节点处接收具有第一电压电平的输入信号，并且在输出节点处提供具有第二电压电平的输出信号。 高电源电压高于第一电压电平。 所述至少一个二极管连接的装置允许输出信号被上拉到大约低于高电源电压的第一二极管电压降和/或被下拉到大约地面上的第二二极管电压降。 第一二极管电压降和第二二极管压降来自至少一个二极管连接的器件。

    Junction varactor for ESD protection of RF circuits
    45.
    发明授权
    Junction varactor for ESD protection of RF circuits 有权
    用于射频电路ESD保护的结型变容二极管

    公开(公告)号：US08334571B2

    公开(公告)日：2012-12-18

    申请号：US12731562

    申请日：2010-03-25

    申请人： Ming-Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Ming-Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H01L23/60 ,  H01L23/64 ,  H01L29/08

    CPC分类号： H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.

    摘要翻译： ESD保护装置包括设置在形成第一二极管的第二半导体类型的衬底中的第一半导体类型的第一阱。 第二半导体类型的第二阱形成在衬底中以与第一阱形成第二二极管。 第一半导体类型的第一多个掺杂区域形成在第一阱的上表面中。 第二半导体类型的第二多个掺杂区域形成在第一阱的上表面中，其与第一阱形成第三二极管。 多个STI区域形成在第一阱的上表面中。 每个STI区域设置在第一和第二半导体类型的掺杂区域之间。 当在第一或第二多个掺杂区域中的一个处接收ESD电压尖峰时，第三二极管提供电流旁路。

    System and method for better testability of OTP memory
    49.
    发明授权
    System and method for better testability of OTP memory 有权
    OTP内存的更好的可测试性的系统和方法

    公开(公告)号：US07843747B2

    公开(公告)日：2010-11-30

    申请号：US12124989

    申请日：2008-05-21

    申请人： Fu-Lung Hsueh ,  Shine Chung ,  Wen-Kuan Fang ,  Po-Hung Chen

    发明人： Fu-Lung Hsueh ,  Shine Chung ,  Wen-Kuan Fang ,  Po-Hung Chen

    IPC分类号： G11C29/00

    CPC分类号： G11C29/08 ,  G11C2216/26

    摘要： A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.

    摘要翻译： 公开了一种用于测试在具有存储器单元阵列的一次可编程（OTP）存储器中执行写入和读取操作的逻辑电路的系统，该系统包括具有与整个存储器单元相同数量的单元格的测试单元列 存储单元阵列的列，一行具有与存储器单元阵列的整行相同数量的单元的测试单元，其中测试单元的列和行首先被写入然后从 在测试操作期间，并且在OTP存储器的非测试操作期间永远不能被访问。

    Electrical fuse circuit for security applications
    50.
    发明授权
    Electrical fuse circuit for security applications 有权
    电熔丝电路用于安全应用

    公开(公告)号：US07821041B2

    公开(公告)日：2010-10-26

    申请号：US11748959

    申请日：2007-05-15

    申请人： Shine Chung ,  Fu-Lung Hsueh ,  Fu-Chieh Hsu

    发明人： Shine Chung ,  Fu-Lung Hsueh ,  Fu-Chieh Hsu

    IPC分类号： H01L29/73

    CPC分类号： G11C17/18

    摘要： A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.

    摘要翻译： 公开了一种熔丝电路，其包括至少一个电熔丝元件，该电熔丝元件具有在电迁移模式下受到应力之后变化的电阻;开关装置，其在熔丝编程电源（VDDQ）之间的预定路径中与电熔丝元件串联连接， 以及用于在编程操作期间选择性地允许通过电熔丝元件的编程电流的低电压电源（GND），以及耦合到所述VDDQ的至少一个外围电路，其中所述外围电路是有效的并且在VDDQ期间从VDDQ引出电流 保险丝编程操作。