利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

74 条记录 (耗时 0.027 秒)

    Built-in Self-test Circuit for Voltage Controlled Oscillators
    1.
    发明申请
    Built-in Self-test Circuit for Voltage Controlled Oscillators 有权
    用于压控振荡器的内置自检电路

    公开(公告)号：US20120286836A1

    公开(公告)日：2012-11-15

    申请号：US13103571

    申请日：2011-05-09

    申请人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H03K3/84

    CPC分类号： G01R31/2824

    摘要： A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

    摘要翻译： 用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。 射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。 此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。 另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

    Switched Capacitor Array for Voltage Controlled Oscillator
    2.
    发明申请
    Switched Capacitor Array for Voltage Controlled Oscillator 审中-公开
    用于压控振荡器的开关电容阵列

    公开(公告)号：US20120286888A1

    公开(公告)日：2012-11-15

    申请号：US13103592

    申请日：2011-05-09

    申请人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H03B5/12 ,  H03H11/00

    CPC分类号： H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/0266

    摘要： A system comprises a voltage controlled oscillator comprising an inductor and a variable capacitor and a switched capacitor array connected in parallel with the variable capacitor. The switched capacitor array further comprises a plurality of capacitor banks wherein a thermometer code is employed to control each capacitor bank. In addition, the switched capacitor array provides N tuning steps for the oscillation frequency of the voltage controlled oscillator when the switched capacitor array is controlled by an n-bit thermometer code.

    摘要翻译： 一种系统包括压控振荡器，其包括电感器和可变电容器以及与可变电容器并联连接的开关电容器阵列。 开关电容器阵列还包括多个电容器组，其中使用温度计代码来控制每个电容器组。 此外，当开关电容器阵列由n位温度计代码控制时，开关电容器阵列为压控振荡器的振荡频率提供N个调谐步骤。

    Through chip coupling for signal transport
    3.
    发明授权
    Through chip coupling for signal transport 有权
    通过芯片耦合进行信号传输

    公开(公告)号：US09397729B2

    公开(公告)日：2016-07-19

    申请号：US12946072

    申请日：2010-11-15

    申请人： Tzu-Jin Yeh ,  Hsieh-Hung Hsieh ,  Jun-De Jin ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Tzu-Jin Yeh ,  Hsieh-Hung Hsieh ,  Jun-De Jin ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H04B5/00

    CPC分类号： H04B5/0081

    摘要： Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit.

    摘要翻译： 芯片耦合用于信号传输，其中在第一集成电路（IC）芯片上的第一线圈和第二IC芯片上的第二线圈之间形成接口。 第一线圈耦合到天线。 第二线圈耦合到放大器电路。 第二线圈不与第一线圈直接接触。 第一线圈和第二线圈在天线和第一放大器电路之间通信地传送信号。

    Built-in self-test circuit for voltage controlled oscillators
    4.
    发明授权
    Built-in self-test circuit for voltage controlled oscillators 有权
    用于压控振荡器的内置自检电路

    公开(公告)号：US08729968B2

    公开(公告)日：2014-05-20

    申请号：US13103571

    申请日：2011-05-09

    申请人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H03L5/00

    CPC分类号： G01R31/2824

    摘要： A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

    摘要翻译： 用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。 射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。 此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。 另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

    Millimeter-wave wideband frequency doubler
    6.
    发明授权
    Millimeter-wave wideband frequency doubler 有权
    毫米波宽带倍频器

    公开(公告)号：US08451033B2

    公开(公告)日：2013-05-28

    申请号：US12967160

    申请日：2010-12-14

    申请人： Po-Yi Wu ,  Hsieh-Hung Hsieh ,  Ho-Hsiang Chen ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Po-Yi Wu ,  Hsieh-Hung Hsieh ,  Ho-Hsiang Chen ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H03B19/00

    CPC分类号： H03B19/00

    摘要： A millimeter-wave wideband frequency doubler stage for use in a distributed frequency doubler includes: a differential input pair of transistors, each transistor having respective gate, drain and source terminals, wherein the source terminals are coupled together to a first power supply node and the drain terminals are coupled together at a first node to a second power supply node; first and second pairs of bandpass gate lines coupled to the gate terminals of the transistors; and a pair of bandpass drain lines coupled to the drain terminals of the transistors.

    摘要翻译： 用于分布式倍频器的毫米波宽带倍频器级包括：差分输入对晶体管，每个晶体管具有相应的栅极，漏极和源极端子，其中源极端子耦合到第一电源节点，并且 漏极端子在第一节点耦合到第二电源节点; 耦合到晶体管的栅极端子的第一和第二对带通栅极线; 以及耦合到晶体管的漏极端子的一对带通漏极线。

    Junction varactor for ESD protection of RF circuits
    7.
    发明授权
    Junction varactor for ESD protection of RF circuits 有权
    用于射频电路ESD保护的结型变容二极管

    公开(公告)号：US08334571B2

    公开(公告)日：2012-12-18

    申请号：US12731562

    申请日：2010-03-25

    申请人： Ming-Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Ming-Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H01L23/60 ,  H01L23/64 ,  H01L29/08

    CPC分类号： H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.

    摘要翻译： ESD保护装置包括设置在形成第一二极管的第二半导体类型的衬底中的第一半导体类型的第一阱。 第二半导体类型的第二阱形成在衬底中以与第一阱形成第二二极管。 第一半导体类型的第一多个掺杂区域形成在第一阱的上表面中。 第二半导体类型的第二多个掺杂区域形成在第一阱的上表面中，其与第一阱形成第三二极管。 多个STI区域形成在第一阱的上表面中。 每个STI区域设置在第一和第二半导体类型的掺杂区域之间。 当在第一或第二多个掺杂区域中的一个处接收ESD电压尖峰时，第三二极管提供电流旁路。

    CMOS millimeter-wave variable-gain low-noise amplifier
    9.
    发明授权
    CMOS millimeter-wave variable-gain low-noise amplifier 有权
    CMOS毫米波可变增益低噪声放大器

    公开(公告)号：US08279008B2

    公开(公告)日：2012-10-02

    申请号：US12851705

    申请日：2010-08-06

    申请人： Hsieh-Hung Hsieh ,  Po-Yi Wu ,  Ho-Hsiang Chen ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Hsieh-Hung Hsieh ,  Po-Yi Wu ,  Ho-Hsiang Chen ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H03G3/30 ,  H03F1/22 ,  H03F3/16

    CPC分类号： H03G1/0029 ,  H03F1/223 ,  H03F3/195 ,  H03F2200/249 ,  H03F2200/318 ,  H03F2200/408 ,  H03F2200/411 ,  H03F2200/451 ,  H03F2200/492 ,  H03G3/3052

    摘要： A low-noise amplifier (LNA) includes a first cascode gain stage coupled to an input node for increasing an amplitude of an RF input signal. A first variable gain network is coupled to the first cascode gain stage and includes a first inductor for boosting a gain of the first cascode gain stage, a first capacitor coupled to the first inductor for blocking a direct current (DC) voltage, and a first switch coupled to the first inductor and to the first capacitor. The first switch is configured to selectively couple the first inductor to the first cascode gain stage in response to a first control signal.

    摘要翻译： 低噪声放大器（LNA）包括耦合到输入节点的第一共源共同增益级，用于增加RF输入信号的幅度。 第一可变增益网络耦合到第一共源共同增益级，并且包括用于升高第一共源共享增益级的增益的第一电感器，耦合到第一电感器以阻止直流（DC）电压的第一电容器，以及第一可变增益网络 开关耦合到第一电感器和第一电容器。 第一开关被配置为响应于第一控制信号选择性地将第一电感器耦合到第一共源共享增益级。

    DIVIDER-LESS PHASE LOCKED LOOP (PLL)
    10.
    发明申请
    DIVIDER-LESS PHASE LOCKED LOOP (PLL) 有权
    无相位锁相环（PLL）

    公开(公告)号：US20140049329A1

    公开(公告)日：2014-02-20

    申请号：US13586033

    申请日：2012-08-15

    申请人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Luan Liu

    发明人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Luan Liu

    IPC分类号： H03L7/099

    CPC分类号： H03K3/0322 ,  H03K3/0315 ,  H03L7/083 ,  H03L7/087 ,  H03L7/089 ,  H03L7/099

    摘要： One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

    摘要翻译： 本文提供了一种用于无分频锁相环（PLL）和相关相位检测器（PD）的技术和系统。 在一些实施例中，接收脉冲相位检测器（pulsePD）信号，压控振荡器正差分（VCOP）信号和压控振荡器负差分（VCON）信号。 基于pulsePD信号，VCOP信号和VCON信号产生用于第一电荷泵（CP）的上升信号和下降信号以及用于第二CP的上升信号和下降信号。 例如，生成CP信号以分别控制第一CP和第二CP。 在一些实施例中，产生CP信号，使得CP有助于调整相对于pulsePD信号的VCON和VCOP信号的零交叉相位。 以这种方式，提供无分频PLL，从而减轻PLL功耗。