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公开(公告)号：US09799753B2
公开(公告)日：2017-10-24
申请号：US15274828
申请日：2016-09-23
Inventor： Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang
IPC: H01L21/84 , H01L29/66 , H01L29/78 , H01L27/108 , H01L27/12 , H01L27/092 , H01L21/8238 , H01L21/265
CPC classification number: H01L29/66795 , H01L21/26513 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/10879 , H01L27/1211 , H01L29/66787 , H01L29/785
Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, an isolation structure over the upper surface of the substrate and surrounding a lower portion of the fin structure, and a first doped region at least partially embedded in an upper portion of the fin structure. The fin structure extends along a first direction. The first doped region has a first type doping different from that of the fin structure.
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公开(公告)号：US09705466B2
公开(公告)日：2017-07-11
申请号：US14630946
申请日：2015-02-25
Inventor： Yen-Jen Chen , Chi-Feng Huang , Hsiao-Chun Lee , Hsieh-Hung Hsieh , Tzu-Jin Yeh
CPC classification number: H03H1/00 , H01L23/585 , H01L23/66 , H01L28/10 , H01L28/40 , H01L2223/6672 , H03H3/00 , H03H7/0115 , H03H2001/0064
Abstract: A semiconductor device comprises a guarded circuit. The semiconductor device also comprises a guard ring surrounding the guarded circuit. The semiconductor device further comprises a resonant circuit coupled with the guard ring. The resonant circuit comprises an input node coupled with the guard ring. The resonant circuit also comprises an inductor. The resonant circuit further comprises a capacitor coupled with the inductor. The resonant circuit additionally comprises a ground node configured to carry a ground voltage. The inductor and the capacitor are coupled between the input node and the ground node.
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公开(公告)号：US20160086948A1
公开(公告)日：2016-03-24
申请号：US14959393
申请日：2015-12-04
Inventor： Chi-Feng Huang , Chia-Chung Chen , Tse-Hua Lu
IPC: H01L27/092 , H01L27/02 , H01L29/06
CPC classification number: H01L27/092 , G01R27/08 , G01R31/02 , H01L22/14 , H01L22/34 , H01L27/0207 , H01L29/0619 , H01L29/0649 , H01L29/1087 , H01L29/7835
Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
Abstract translation: 确定高压PMOS（HVPMOS）器件的可靠性的方法包括确定HVPMOS器件的体电阻，以及基于体电阻来评估HVPMOS器件的可靠性。
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公开(公告)号：US20140252542A1
公开(公告)日：2014-09-11
申请号：US13792306
申请日：2013-03-11
Inventor： Hsiao-Chun Lee , Victor Chiang Liang , Chi-Feng Huang
IPC: H01L49/02
CPC classification number: H01L28/10 , H01L23/522 , H01L23/5227 , H01L2924/0002 , H01L2924/00
Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes an inductor formed on a substrate and configured to be operable with a current of a frequency; and dummy metal features configured between the inductor and the substrate, the dummy metal features having a first width less than 2 times of a skin depth associated with the frequency.
Abstract translation: 本发明提供一种半导体器件。 半导体器件包括形成在衬底上并被配置为可与频率电流一起工作的电感器; 以及配置在电感器和衬底之间的虚拟金属特征，虚拟金属特征具有小于与频率相关联的皮肤深度的2倍的第一宽度。
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公开(公告)号：US20140239364A1
公开(公告)日：2014-08-28
申请号：US14263744
申请日：2014-04-28
Inventor： Chi-Feng Huang , Chia-Chung Chen
CPC classification number: H01L29/66174 , H01L27/0808 , H01L27/0811 , H01L29/93 , H01L29/94
Abstract: Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.
Abstract translation: 公开了MOS变容二极管结构的装置和方法。 提供了一种装置，包括限定在半导体衬底的一部分中的有源区; 在有源区域中延伸到半导体衬底中的掺杂阱区; 在所述掺杂阱区域上平行布置的至少两个栅极结构; 源极和漏极区域，设置在形成在栅极结构的相对侧上的阱区域中; 栅极连接器，形成在覆盖所述至少两个栅极结构并电耦合所述至少两个栅极结构的第一金属层中; 源极和漏极连接器，其形成在第二金属层中并电耦合到源极和漏极区域; 以及将第二金属层中的源极和漏极连接器与形成在第一金属层中的栅极连接器分开的层间电介质材料。 公开了形成结构的方法。
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Patent Agency Ranking
公开(公告)号：US20240290652A1
公开(公告)日：2024-08-29
申请号：US18657752
申请日：2024-05-07
Inventor： Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang , Chung-Hao Chu , Ching-Yu Yang
IPC: H01L21/768 , H01L21/324 , H01L29/08 , H01L29/165 , H01L29/45 , H01L29/66 , H01L29/78
CPC classification number: H01L21/76814 , H01L21/324 , H01L21/76805 , H01L21/76843 , H01L21/76895 , H01L29/0847 , H01L29/165 , H01L29/45 , H01L29/7833 , H01L29/7848 , H01L29/665 , H01L29/6656
Abstract: A semiconductor device includes a first gate stack structure over a substrate, a source/drain epitaxial layer, a lightly doped region, and a silicide region. The source/drain epitaxial layer is disposed in the substrate and adjacent to the first gate stack structure. The lightly doped region is located in the substrate to be electrically connected to the source/drain epitaxial layer. The lightly doped region includes a first portion protrudes from a sidewall of the source/drain epitaxial layer. The silicide region is in contact with a top surface and sidewalls of a top portion of the source/drain epitaxial layer and a top surface of the first portion of the lightly doped region. The top portion of the source/drain epitaxial layer is higher than the top surface of the first portion of the lightly doped region.
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公开(公告)号：US11990474B2
公开(公告)日：2024-05-21
申请号：US18151990
申请日：2023-01-09
Inventor： Shu Fang Fu , Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Fu-Huan Tsai
IPC: H01L27/088 , H01L21/8238 , H01L27/02 , H01L27/092 , H01L29/10 , H01L29/78 , H03K3/03
CPC classification number: H01L27/0886 , H01L21/823807 , H01L21/823821 , H01L21/823871 , H01L21/823878 , H01L27/0207 , H01L27/092 , H01L27/0924 , H01L29/1041 , H01L29/7835 , H01L29/785 , H01L21/823814 , H03K3/0315
Abstract: A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.
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公开(公告)号：US11552076B2
公开(公告)日：2023-01-10
申请号：US16938528
申请日：2020-07-24
Inventor： Shu Fang Fu , Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Fu-Huan Tsai
IPC: H01L27/088 , H01L27/02 , H01L27/092 , H01L29/10 , H01L29/78 , H01L21/8238 , H03K3/03
Abstract: A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.
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公开(公告)号：US10833082B2
公开(公告)日：2020-11-10
申请号：US16599929
申请日：2019-10-11
Inventor： Chia-Chung Chen , Chi-Feng Huang , Tse-Hua Lu
Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
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公开(公告)号：US10804228B2
公开(公告)日：2020-10-13
申请号：US16400419
申请日：2019-05-01
Inventor： Chia-Chung Chen , Chi-Feng Huang , Shu Fang Fu , Tzu-Jin Yeh , Chewn-Pu Jou
IPC: H01L21/762 , H01L29/417 , H01L29/78 , H01L21/761 , H01L23/66 , H01L29/66 , H01L29/10 , H01L21/8238 , H01L21/265 , H01L27/06 , H01L49/02 , H01L29/06 , H01L29/45
Abstract: A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.
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