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    Phase shifter circuit, phase shifter layout and method of forming the same
    1.
    发明授权
    Phase shifter circuit, phase shifter layout and method of forming the same 有权

    公开(公告)号：US12229488B2

    公开(公告)日：2025-02-18

    申请号：US17833436

    申请日：2022-06-06

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chi-Hsien Lin ,  Ho-Hsiang Chen ,  Hsien-Yuan Liao ,  Tzu-Jin Yeh ,  Ying-Ta Lu

    IPC: G03F1/70 ,  G03F1/36 ,  G06F30/398 ,  H03H11/20

    Abstract: A phase shifter includes a first transistor and a second transistor. The first transistor includes a first gate terminal configured to receive a first voltage. The first transistor is configured to adjust at least a resistance or a first capacitance of the phase shifter responsive to the first voltage. The second transistor is coupled to the first transistor. The second transistor includes a second gate terminal configured to receive a second voltage. The second transistor is configured to adjust a second capacitance of the phase shifter responsive to the second voltage. The second gate terminal includes a first polysilicon portion and a second polysilicon portion extending in a first direction. The first polysilicon portion and the second polysilicon portion are positioned along opposite edges of an active region of the first transistor and the second transistor.

    Semiconductor device and method of forming the same
    4.
    发明授权
    Semiconductor device and method of forming the same 有权

    公开(公告)号：US10553721B2

    公开(公告)日：2020-02-04

    申请号：US15705469

    申请日：2017-09-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Chia-Chung Chen

    IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092

    Abstract: A semiconductor device includes a plurality of fins over a substrate. Each fin of the plurality of fins extends in a first direction substantially perpendicular to a bottom surface of the substrate, and each fin of the plurality of fins comprises a first doped region having a first dopant type. The semiconductor device further includes an isolation region over the substrate between a first fin of the plurality of fins and a second fin of the plurality of fins adjacent to the first fin. The semiconductor device further includes a second doped region extends continuously across the isolation region, the second doped region extends into each fin of the plurality of fins, and a dimension of the second doped region in the isolation region in a second direction perpendicular to the first direction is less than a dimension of the at least one isolation region in the second direction.

    Inductor shielding structure, integrated circuit including the same and method of forming the integrated circuit
    7.
    发明授权
    Inductor shielding structure, integrated circuit including the same and method of forming the integrated circuit 有权
    电感器屏蔽结构，集成电路包括与集成电路相同的形成方法

    公开(公告)号：US09484312B2

    公开(公告)日：2016-11-01

    申请号：US14600634

    申请日：2015-01-20

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chi-Hsien Lin ,  Hsien-Yuan Liao ,  Ying-Ta Lu ,  Ho-Hsiang Chen ,  Tzu-Jin Yeh

    IPC: H01L23/52 ,  H01L23/552 ,  H01L49/02 ,  H01L23/522

    CPC classification number: H01L23/552 ,  H01L23/5225 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/14

    Abstract: An inductor shielding structure includes a first conductive layer including a plurality of first conductive lines having a first width and a plurality of second conductive lines having a second width. The inductor shielding structure further includes a second conductive layer over the first conductive layer. The second conductive layer includes at least one third conductive line having a third width and a plurality of fourth conductive lines having a fourth width. Each conductive line of the at least one third conductive line is parallel to each conductive line of the plurality of first conductive lines. Each conductive line of the plurality of fourth conductive lines is parallel to each conductive line of the plurality of second conductive lines. The first width is different from the second width, or the third width is different from the fourth width.

    Abstract translation: 电感器屏蔽结构包括第一导电层，其包括具有第一宽度的多个第一导电线和具有第二宽度的多个第二导线。 电感器屏蔽结构还包括在第一导电层上的第二导电层。 第二导电层包括具有第三宽度的至少一个第三导线和具有第四宽度的多个第四导线。 所述至少一个第三导线的每个导线平行于所述多个第一导线中的每条导线。 多个第四导线中的每个导线平行于多个第二导线中的每条导线。 第一宽度与第二宽度不同，或者第三宽度不同于第四宽度。

    Built-in Self-test Circuit for Voltage Controlled Oscillator
    8.
    发明申请
    Built-in Self-test Circuit for Voltage Controlled Oscillator 有权
    用于压控振荡器的内置自检电路

    公开(公告)号：US20140225676A1

    公开(公告)日：2014-08-14

    申请号：US14252886

    申请日：2014-04-15

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC: H03L7/06

    CPC classification number: G01R31/2824 ,  H03L5/00

    Abstract: A device comprises a radio frequency peak detector configured to receive an ac signal from a voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector and a feedback control unit coupled between an output of the radio frequency peak detector and an input of the voltage controlled oscillator.

    Abstract translation: 一种设备包括：射频峰值检测器，被配置为从压控振荡器接收交流信号，并在射频峰值检测器的输出处产生与ac信号成比例的直流值，以及反馈控制单元，其耦合在无线电 频率峰值检测器和压控振荡器的输入。

    Power amplifiers
    9.
    发明授权
    Power amplifiers 有权

    公开(公告)号：US12132450B2

    公开(公告)日：2024-10-29

    申请号：US17695500

    申请日：2022-03-15

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Wen-Sheng Chen ,  En-Hsiang Yeh ,  Tzu-Jin Yeh

    IPC: H03F1/30 ,  H03F3/24 ,  H04B1/16 ,  H04B1/18

    CPC classification number: H03F1/30 ,  H03F3/245 ,  H04B1/1607 ,  H04B1/18

    Abstract: A power amplifier structure includes at least one power amplifier circuit. The power amplifier circuit includes a transistor of a first type connected in series with a transistor of a second type connected between the same voltage supply. In a non-limiting nonexclusive example, an n-type transistor is connected in series with a p-type transistor connected between Vdd. The power amplifier structure can include two amplifier circuits configured in a differential amplifier structure. The differential amplifier structure includes two amplifier circuits operably connected in parallel between the same voltage supply.

    Test circuit and method
    10.
    发明授权
    Test circuit and method 有权

    公开(公告)号：US11768235B2

    公开(公告)日：2023-09-26

    申请号：US18151959

    申请日：2023-01-09

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Hsieh-Hung Hsieh ,  Yen-Jen Chen ,  Tzu-Jin Yeh

    IPC: G01R31/28

    CPC classification number: G01R31/2884 ,  G01R31/2853 ,  G01R31/2879

    Abstract: An IC includes a plurality of pads at a top surface of a semiconductor wafer, an amplifier configured to receive a first AC signal at an input terminal, and output a second AC signal at an output terminal, a first detection circuit coupled to the input terminal and configured to output a first DC voltage to a first pad of the plurality of pads responsive to the first AC signal, and a second detection circuit coupled to the output terminal and configured to output a second DC voltage to a second pad of the plurality of pads responsive to the second AC signal.

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