公开(公告)号：US11652148B2

公开(公告)日：2023-05-16

申请号：US17471736

申请日：2021-09-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Song-Fu Liao ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L21/28 ,  H01L29/66 ,  H01L27/11597 ,  H01L29/786 ,  H01L21/443 ,  H01L21/02 ,  H01L21/4757

CPC classification number: H01L29/40111 ,  H01L27/11597 ,  H01L29/66969 ,  H01L21/02642 ,  H01L21/443 ,  H01L21/47573 ,  H01L29/7869

Abstract: A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multiple source/drain segments each connected to corresponding ones of the channel sub-layers.

公开(公告)号：US20230143625A1

公开(公告)日：2023-05-11

申请号：US17570028

申请日：2022-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Song-Fu Liao ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11585

CPC classification number: H01L29/40111 ,  H01L29/6684 ,  H01L29/78391 ,  H01L27/11585

Abstract: In some embodiments, the present disclosure relates to a method for forming an integrated circuit (IC), including forming a first electrode layer having a first metal over a substrate, performing a first atomic layer deposition (ALD) pulse that exposes the first electrode layer to oxygen atoms, exposing the first electrode layer to a first temperature, the first temperature causing the first electrode layer to react with the oxygen atoms to form a seed structure over the first electrode layer, and performing a series of ALD pulses at a second temperature to form a ferroelectric structure over the seed structure. The second temperature is less than the first temperature and the ferroelectric structure is configured to store a data state.

公开(公告)号：US11637010B2

公开(公告)日：2023-04-25

申请号：US16895800

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L29/06 ,  H01L21/764 ,  H01L23/528

Abstract: The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

公开(公告)号：US20220359544A1

公开(公告)日：2022-11-10

申请号：US17873236

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L21/28 ,  H01L29/51 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.

公开(公告)号：US20220254678A1

公开(公告)日：2022-08-11

申请号：US17729429

申请日：2022-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yen Huang ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Ting-Ya Lo

IPC: H01L21/768 ,  H01L23/532

Abstract: Some embodiments relate to a semiconductor structure including a conductive wire disposed within a first dielectric structure. An etch stop layer overlies the first dielectric structure. A dielectric capping layer is disposed between an upper surface of the conductive wire and the etch stop layer. An upper dielectric layer is disposed along sidewalls of the conductive wire and an upper surface of the etch stop layer. The upper dielectric layer contacts an upper surface of the dielectric capping layer and has a top surface vertically above the etch stop layer.

公开(公告)号：US11328991B2

公开(公告)日：2022-05-10

申请号：US16913515

申请日：2020-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

公开(公告)号：US10943867B2

公开(公告)日：2021-03-09

申请号：US16450788

申请日：2019-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/40 ,  H01L21/768 ,  H01L23/532 ,  H01L21/322 ,  H01L23/528

Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

公开(公告)号：US20200328152A1

公开(公告)日：2020-10-15

申请号：US16913515

申请日：2020-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

公开(公告)号：US10700000B2

公开(公告)日：2020-06-30

申请号：US15601305

申请日：2017-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/522 ,  H01L21/02 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

公开(公告)号：US20190311993A1

公开(公告)日：2019-10-10

申请号：US16450788

申请日：2019-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/322

Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.