公开(公告)号：US20250094221A1

公开(公告)日：2025-03-20

申请号：US18970449

申请日：2024-12-05

Applicant: Texas Instruments Incorporated

Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Jesse Gregory Villarreal, JR. ,  Lucas Carl Weaver ,  Brijesh Jadav ,  Niraj Nandan

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/54

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

公开(公告)号：US12244979B2

公开(公告)日：2025-03-04

申请号：US17983905

申请日：2022-11-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jing-Fei Ren ,  Hrushikesh Garud ,  Rajasekhar Allu ,  Gang Hua ,  Niraj Nandan ,  Mayank Mangla ,  Mihir Narendra Mody

IPC: H04N9/64 ,  G06T7/00 ,  G06T7/90

Abstract: Various embodiments disclosed herein relate to defective pixel detection and correction, and more specifically to using threshold functions based on color channels to compare pixel values to threshold values. A method is provided herein that comprises identifying a color channel of an image pixel in a frame and identifying a threshold function based at least on the color channel. The method further comprises applying the threshold function to one or more nearest-neighbor values to obtain a threshold value and determining whether a corresponding sensor pixel is defective based at least on a comparison of the image pixel to the threshold value.

公开(公告)号：US12210449B2

公开(公告)日：2025-01-28

申请号：US18426053

申请日：2024-01-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishan Govindarajan ,  Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha

IPC: G06F12/02

Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a transaction handling block that dynamically maps the most frequently accessed memory regions into faster access memory. The technique creates shadow copies of the most frequently accessed memory regions in the faster access memory, which is associated with lower latency. The regions for which shadow copies are provided are updated dynamically based on use. The technique is flexible for different memory hierarchies.

公开(公告)号：US12164956B2

公开(公告)日：2024-12-10

申请号：US17349310

申请日：2021-06-16

Applicant: Texas Instruments Incorporated

Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Jesse Gregory Villarreal, Jr. ,  Lucas Carl Weaver ,  Brijesh Jadav ,  Niraj Nandan

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/54

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

公开(公告)号：US12112399B2

公开(公告)日：2024-10-08

申请号：US17520861

申请日：2021-11-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj Nandan ,  Rajasekhar Reddy Allu ,  Mihir Narendra Mody

IPC: G06F9/50 ,  G06F9/54 ,  G06T1/60

CPC classification number: G06T1/60 ,  G06F9/5027 ,  G06F9/5066 ,  G06F9/544

Abstract: A lens distortion correction function operates by backmapping output images to the uncorrected, distorted input images. As a vision image processor completes processing on the image data lines needed for the lens distortion correction function to operate on a group of output, undistorted image lines, the lens distortion correction function begins processing the image data. This improves image processing pipeline delays by overlapping the operations. The vision image processor provides output image data to a circular buffer in SRAM, rather than providing it to DRAM. The lens distortion correction function operates from the image data in the circular buffer. By operating from the SRAM circular buffer, access to the DRAM for the highly fragmented backmapping image data read operations is removed, improving available DRAM bandwidth. By using a circular buffer, less space is needed in the SRAM. The improved memory operations further improve the image processing pipeline delays.

公开(公告)号：US20240126560A1

公开(公告)日：2024-04-18

申请号：US18395697

申请日：2023-12-25

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Denis Roland Beaudoin ,  Gregory Raymond Shurtz ,  Santhanakrishnan Badri Narayanan ,  Mark Adrian Bryans ,  Mihir Narendra Mody ,  Jason A.T. Jones ,  Jayant Thakur

IPC: G06F9/4401 ,  G06F13/28 ,  H04L45/00 ,  H04L47/32 ,  H04L49/351

CPC classification number: G06F9/4418 ,  G06F9/4406 ,  G06F13/28 ,  H04L45/54 ,  H04L45/66 ,  H04L47/32 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US20240054601A1

公开(公告)日：2024-02-15

申请号：US18383576

申请日：2023-10-25

Applicant: Texas Instruments Incorporated

Inventor： Shashank Dabral ,  Gang Hua ,  Mihir Narendra Mody

IPC: G06T3/40 ,  H04N5/33 ,  H01L27/146 ,  H04N25/13

CPC classification number: G06T3/4015 ,  H04N5/33 ,  H01L27/14649 ,  H01L27/14621 ,  H04N25/134 ,  H04N25/131

Abstract: A method for processing RGB-Infrared (RGB-IR) sensor data is provided that includes receiving a raw RGB-IR image, determining whether to process the raw RGB-IR image in day mode or night mode, generating, when day mode is determined, an infrared (IR) subtracted raw Bayer image from the raw RGB-IR image and processing the IR subtracted raw Bayer image in an image signal processor (ISP), and generating, when night mode is determined, an IR image from the raw RGB-IR image.

公开(公告)号：US11880333B2

公开(公告)日：2024-01-23

申请号：US17314313

申请日：2021-05-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jason A. T. Jones ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Kishon Vijay Abraham Israel Vijayponraj ,  Bradley Douglas Cobb ,  Sanand Prasad ,  Gregory Raymond Shurtz ,  Martin Jeffrey Ambrose ,  Jayant Thakur

IPC: G06F15/78 ,  G06F13/10

CPC classification number: G06F15/7807 ,  G06F13/10 ,  G06F15/7864

Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).

公开(公告)号：US11861891B2

公开(公告)日：2024-01-02

申请号：US17483713

申请日：2021-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Manoj Koul

IPC: G06V10/98 ,  G06F11/07 ,  G06T5/00 ,  G06V10/36 ,  G06T7/00 ,  H04L41/0677

CPC classification number: G06V10/98 ,  G06F11/079 ,  G06F11/0736 ,  G06F11/0751 ,  G06F11/0772 ,  G06T5/00 ,  G06V10/36 ,  G06T7/0002 ,  H04L41/0677

Abstract: Methods, apparatus, and articles of manufacture providing an efficient safety mechanism for signal processing hardware are disclosed. An example apparatus includes an input interface to receive an input signal; a hardware accelerator to process the input signal, the hardware accelerator including: unprotected memory to store non-critical data corresponding to the input signal; and protected memory to store critical data corresponding to the input signal; and an output interface to transmit the processed input signal.

公开(公告)号：US11853857B2

公开(公告)日：2023-12-26

申请号：US16889853

申请日：2020-06-02

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Veeramanikandan Raju ,  Chaitanya Ghone ,  Deepak Poddar

IPC: G06N3/04 ,  G06N3/088 ,  H04L9/40 ,  G06N3/045

CPC classification number: G06N3/04 ,  G06N3/045 ,  G06N3/088 ,  H04L63/0435 ,  H04L63/0464

Abstract: A convolutional neural network (CNN)-based signal processing includes receiving of an encrypted output from a first layer of a multi-layer CNN data. The received encrypted output is subsequently decrypted to form a decrypted input to a second layer of the multi-layer CNN data. A convolution of the decrypted input with a corresponding decrypted weight may generate a second layer output, which may be encrypted and used as an encrypted input to a third layer of the multi-layer CNN data.