公开(公告)号：US20220310816A1

公开(公告)日：2022-09-29

申请号：US17406937

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Hsieh Wong ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66

Abstract: Embodiments utilize a two layer inner spacer structure during formation of the inner spacers of a nano-FET device. The materials of the first inner spacer layer and second inner spacer layer can be selected to have a mismatch in their coefficients of thermal expansion (CTE). As the structure cools after deposition, the inner spacer layer which has a larger CTE will exhibit compressive stress on the other inner spacer layer, however, because the two layers have a common interface, the layer with the smaller CTE will exhibit a counter acting tensile stress.

公开(公告)号：US20220223718A1

公开(公告)日：2022-07-14

申请号：US17706296

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bone-Fong Wu ,  Chih-Hao Yu ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.

公开(公告)号：US12278145B2

公开(公告)日：2025-04-15

申请号：US17460528

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Lee ,  Chii-Horng Li ,  Bang-Ting Yan ,  Bo-Yu Lai ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a multilayer source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a source/drain barrier material is deposited using a bottom-up deposition process at the bottom of the opening to a level below the multilayer stack. A multilayer source/drain region is formed over the source/drain barrier material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the multilayer source/drain region being electrically coupled to the stack of nanostructures.

公开(公告)号：US20240379822A1

公开(公告)日：2024-11-14

申请号：US18780150

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bone-Fong Wu ,  Chih-Hao Yu ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.

公开(公告)号：US12125889B2

公开(公告)日：2024-10-22

申请号：US17465665

申请日：2021-09-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yeh Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Da-Wen Lin

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/0665 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

公开(公告)号：US20240186180A1

公开(公告)日：2024-06-06

申请号：US18438653

申请日：2024-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Lun Chang ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Yuan-Ching Peng

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/762 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/7682 ,  H01L21/7624 ,  H01L21/76804 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/5329 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/66742 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/78696

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

公开(公告)号：US11855225B2

公开(公告)日：2023-12-26

申请号：US17127343

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yeh Chen ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78696

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.

公开(公告)号：US20230065318A1

公开(公告)日：2023-03-02

申请号：US17461412

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Han Fan ,  Wei-Yang Lee ,  Tzu-Hua Chiu ,  Chia-Pin Lin

IPC: H01L29/40 ,  H01L29/417 ,  H01L21/768

Abstract: A method of forming a semiconductor including forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate. The method further includes forming a dummy fin adjacent to the source/drain feature and adjacent to the semiconductor layer stack. The method further includes performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, where the first trench extends from the dummy fin to the source/drain feature. The method further includes forming a first dielectric layer in the first trench and replacing a second portion of the dummy fin with a source/drain contact.

公开(公告)号：US20230064735A1

公开(公告)日：2023-03-02

申请号：US17460528

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Lee ,  Chii-Horng Li ,  Bang-Ting Yan ,  Bo-Yu Lai ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a multilayer source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a source/drain barrier material is deposited using a bottom-up deposition process at the bottom of the opening to a level below the multilayer stack. A multilayer source/drain region is formed over the source/drain barrier material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the multilayer source/drain region being electrically coupled to the stack of nanostructures.

公开(公告)号：US20220367727A1

公开(公告)日：2022-11-17

申请号：US17814132

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Lun Chang ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Yuan-Ching Peng

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L23/528

Abstract: Semiconductor devices including backside vias with enlarged backside portions and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; a first dielectric layer on a backside of the first device layer; a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a backside interconnect structure on a backside of the first dielectric layer and the first contact, the first contact including a first portion having first tapered sidewalls and a second portion having second tapered sidewalls, widths of the first tapered sidewalls narrowing in a direction towards the backside interconnect structure, and widths of the second tapered sidewalls widening in a direction towards the backside interconnect structure.