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    Techniques based on electromigration characteristics of cell interconnect
    41.
    发明授权
    Techniques based on electromigration characteristics of cell interconnect 有权

    公开(公告)号：US10157254B2

    公开(公告)日：2018-12-18

    申请号：US15361970

    申请日：2016-11-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Nan Yang ,  Chung-Hsing Wang ,  Yi-Kan Cheng ,  Kumar Lalgudi

    IPC: G06F17/50 ,  H01L23/528 ,  H03K5/15

    Abstract: In some embodiments, the present disclosure relates to a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first clock line having a first line width and being arranged at a first height as measured from an upper surface of the semiconductor substrate. The clock tree structure also includes a second clock line having a second line width, which differs from the first line width. The second clock line is arranged at a second height as measured from the upper surface of the semiconductor substrate and the second height is equal to the first height. The first line width can be directly proportional to a first current level for the first clock line and the second line width can be directly proportional to a second current level for the second clock line.

    CONSTRAINED CELL PLACEMENT
    42.
    发明申请
    CONSTRAINED CELL PLACEMENT 审中-公开

    公开(公告)号：US20180330034A1

    公开(公告)日：2018-11-15

    申请号：US15878818

    申请日：2018-01-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Yuan-Te Hou

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F2217/06

    Abstract: The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.

    Method and system for designing Fin-FET semiconductor device
    44.
    发明授权
    Method and system for designing Fin-FET semiconductor device 有权
    Fin-FET半导体器件的设计方法和系统

    公开(公告)号：US09141745B2

    公开(公告)日：2015-09-22

    申请号：US14068064

    申请日：2013-10-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Min Fu ,  Yung-Fong Lu ,  Chung-Hsing Wang

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: A method includes providing a first layout of a semiconductor device comprising a plurality of cells representing circuit elements, and providing a cell library comprising a plurality of cells in a processor. The circuit elements comprise a plurality of fin field effect transistors (Fin-FETs). Each of the plurality of cells in the cell library is displayed with a respectively different marker indicating a respective fin height. The method further includes generating a second layout for the semiconductor device to be fabricated, by placing or replacing at least one cell from the cell library in a respective location in the first layout. The at least one cell from the cell library comprises a Fin-FET with a respective fin height different from an adjacent Fin-FET in the second layout.

    Abstract translation: 一种方法包括提供包括表示电路元件的多个单元的半导体器件的第一布局，以及在处理器中提供包括多个单元的单元库。 电路元件包括多个鳍式场效应晶体管（Fin-FET）。 单元库中的多个单元格中的每个单元都显示有指示相应的翅片高度的分别不同的标记。 该方法还包括通过在第一布局中的相应位置放置或替换来自单元库的至少一个单元来产生要制造的半导体器件的第二布局。 来自电池库的至少一个电池包括在第二布局中具有与相邻Fin-FET不同的散热片高度的Fin-FET。

    PATTERN MATCHING BASED PARASITIC EXTRACTION WITH PATTERN REUSE
    45.
    发明申请
    PATTERN MATCHING BASED PARASITIC EXTRACTION WITH PATTERN REUSE 有权
    基于模式匹配的PARASITIC EXTRACTION WITH PATTERN REUSE

    公开(公告)号：US20140137062A1

    公开(公告)日：2014-05-15

    申请号：US13677380

    申请日：2012-11-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ping-Hung Yuh ,  Hsin-Yun Lin ,  Cheng-I Huang ,  Chung-Hsing Wang

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G06F17/5036 ,  G06F17/5081

    Abstract: The present disclosure relates to a method and apparatus for accurate RC extraction. A pattern database is configured to store layout patterns and their associated 3D extraction parameters. A pattern-matching tool is configured to partition a design into a plurality of patterns, and to search the pattern database for a respective pattern and associated 3D extraction parameters. If the respective pattern is already stored in the pattern database, then the associated 3D extraction parameters stored in the database are assigned to the respective pattern without the need to extract the respective pattern. If the respective pattern is not stored in the pattern database, then the extraction tool extracts the pattern and stores its associated 3D extraction parameters in the pattern database for future use. In this manner a respective pattern is extracted only once for a given design or plurality of designs. Moreover, the extraction result may be applied multiple times for a given design simultaneously, speeding up computation time. The extraction result may also be applied to a plurality of designs simultaneously.

    Abstract translation: 本公开涉及一种用于精确RC提取的方法和装置。 模式数据库被配置为存储布局模式及其相关的3D提取参数。 模式匹配工具被配置为将设计分割成多个模式，并且搜索模式数据库中的相应模式和相关联的3D提取参数。 如果相应的图案已经存储在图案数据库中，则存储在数据库中的相关3D提取参数被分配给相应的图案，而不需要提取相应的图案。 如果相应的图案不存储在图案数据库中，则提取工具提取图案并将其相关联的3D提取参数存储在图案数据库中以供将来使用。 以这种方式，对于给定的设计或多个设计，相应的图案仅被提取一次。 此外，提取结果可以同时应用于给定设计的多次，从而加快了计算时间。 提取结果也可以同时应用于多个设计。

    DIAGONAL TORUS NETWORK
    47.
    发明申请
    DIAGONAL TORUS NETWORK 有权

    公开(公告)号：US20230066045A1

    公开(公告)日：2023-03-02

    申请号：US17461225

    申请日：2021-08-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jerry Chang Jui Kao ,  Huang-Yu Chen ,  Yung-Chen Chien ,  Tzu-Ying Lin ,  Wei-Hsiang Ma ,  Chung-Hsing Wang

    IPC: G06F15/173 ,  G06F15/17

    Abstract: A device is disclosed that includes multiple channels and multiple processing nodes. Each processing node includes input/output (I/O) ports coupled to the channels and channel control modules coupled to the I/O ports. Each processing node is configured to select, by the channel control module in a first operation, a first I/O port of the I/O ports; communicate a first message, via the first I/O port, to a first processing node over a first channel or a second processing node over a second channel orthogonal to the first channel in a logic representation; select, by the channel control module in a second operation, a second I/O port of the I/O ports; and communicate a second message, via the second I/O port, to a third processing node over a third channel extending in a diagonal direction and non-orthogonal to the first and second channels in the logic representation.

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