公开(公告)号：US20220376078A1

公开(公告)日：2022-11-24

申请号：US17813653

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gerben Doornbos ,  Marcus Johannes Henricus van Dal ,  Georgios Vellianitis

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/04 ,  H01L29/207 ,  H01L27/1159

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

公开(公告)号：US11387362B2

公开(公告)日：2022-07-12

申请号：US16426634

申请日：2019-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Van Dal

IPC: H01L29/78 ,  H01L21/84 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/165 ,  H01L29/786

Abstract: A semiconductor device includes a gate-all-around field effect transistor (GAA FET). The GAA FET includes channel regions made of a first semiconductor material disposed over a bottom fin layer made of a second semiconductor material, and a source/drain region made of a third semiconductor material. The first semiconductor material is Si1-xGex, where 0.9≤x≤1.0, and the second semiconductor material is Si1-yGey, where y

公开(公告)号：US11302801B2

公开(公告)日：2022-04-12

申请号：US16886606

申请日：2020-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Georgios Vellianitis

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/8258 ,  H01L27/092 ,  H01L21/762

Abstract: A semiconductor device includes plural semiconductor fins and a gate structure over at least one of the semiconductor fins. The semiconductor fins have parallelogram top surfaces, and the parallelogram top surface has two acute interior angles and two obtuse interior angles. Two of the semiconductor fins are arranged along crystallographic direction, and two of the semiconductor fins are arranged along crystallographic direction.

公开(公告)号：US20210376108A1

公开(公告)日：2021-12-02

申请号：US16888393

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gerben Doornbos ,  Marcus Johannes Henricus van Dal ,  Georgios Vellianitis

IPC: H01L29/51 ,  H01L29/207 ,  H01L29/04 ,  H01L29/66

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

公开(公告)号：US20210375934A1

公开(公告)日：2021-12-02

申请号：US17130609

申请日：2020-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Mauricio Manfrini ,  Georgios Vellianitis

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.

公开(公告)号：US11189490B2

公开(公告)日：2021-11-30

申请号：US16399669

申请日：2019-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Georgios Vellianitis

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  H01L29/04 ,  H01L29/423 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84

Abstract: In a method of manufacturing a semiconductor device, a single crystal oxide layer is formed over a substrate. After the single crystal oxide layer is formed, an isolation structure to define an active region is formed. A gate structure is formed over the single crystal oxide layer in the active region. A source/drain structure is formed.

公开(公告)号：US20210296442A1

公开(公告)日：2021-09-23

申请号：US17340240

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Martin Christopher Holland ,  Georgios Vellianitis

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/775

Abstract: Provided herein are semiconductor structures that include germanium and have a germanium nitride layer on the surface, as well as methods of forming the same. The described structures include nanowires and fins. Methods of the disclosure include metal-organic chemical vapor deposition with a germanium precursor. The described methods also include using a N2H4 vapor.

公开(公告)号：US11069813B2

公开(公告)日：2021-07-20

申请号：US16588453

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Blandine Duriez ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L21/268 ,  H01L29/786 ,  H01L21/285 ,  H01L29/45 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/324 ,  H01L21/311

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes forming conductive plugs in the source/drain contact openings. The method further includes depositing a light blocking layer over the conductive plugs and the at least one dielectric layer. The method further includes etching the light blocking layer to expose the conductive plugs. The method further includes directing a laser irradiation to the conductive plugs and the light blocking layer. The laser irradiation is configured to activate dopants in the source/drain contact regions.

公开(公告)号：US11056568B2

公开(公告)日：2021-07-06

申请号：US16449837

申请日：2019-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Georgios Vellianitis ,  Gerben Doornbos

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  B82Y10/00 ,  H01L21/8234 ,  H01L29/10

Abstract: A method is provided. First and second fins are etched to form a first recess over the etched first fin and a second recess over the etched second fin. A first composite fin and a second composite fin are concurrently epitaxially grown respectively in the first recess and the second recess. The first composite fin includes a plurality of nanowire channels and at least one sacrificial layer. The second composite fin includes at least one nanowire channel and at least one sacrificial layer. A number of the plurality of nanowire channels of the first composite fin is greater than a number of the at least one nanowire channel of the second composite fin. A dielectric material is recessed to expose at least a portion of the first composite fin and at least a portion of the second composite fin.

公开(公告)号：US11004958B2

公开(公告)日：2021-05-11

申请号：US16271964

申请日：2019-02-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Timothy Vasen

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/08 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.